From 0bfbb218378a7bc17d2b92e46686693e77667d19 Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Thu, 23 Sep 2010 11:02:48 +0000 Subject: [PATCH] arm-linux: zero out the least significant bit of R15 that we ptrace into the child, so as to be a legitimate instruction address in both ARM and Thumb mode. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11375 --- coregrind/m_debugger.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/coregrind/m_debugger.c b/coregrind/m_debugger.c index 76861031b6..eaf80d1892 100644 --- a/coregrind/m_debugger.c +++ b/coregrind/m_debugger.c @@ -223,7 +223,10 @@ static Int ptrace_setregs(Int pid, VexGuestArchState* vex) uregs.ARM_ip = vex->guest_R12; uregs.ARM_sp = vex->guest_R13; uregs.ARM_lr = vex->guest_R14; - uregs.ARM_pc = vex->guest_R15T; + // Remove the T bit from the bottom of R15T. It will get shipped + // over in CPSR.T instead, since LibVEX_GuestARM_get_cpsr copies + // it from R15T[0]. + uregs.ARM_pc = vex->guest_R15T & 0xFFFFFFFE; uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex); return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); -- 2.47.2