From 0d1987fb5c63d96768d47064c7a69bc8b038aa89 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 5 Aug 2020 00:18:38 +0000 Subject: [PATCH] Daily bump. --- gcc/ChangeLog | 66 +++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 14 +++++++++ 3 files changed, 81 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d75296d982c1..d6dde8d33f56 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,69 @@ +2020-08-04 Matthew Malcomson + + * config/aarch64/aarch64-protos.h (aarch64_indirect_call_asm): + New declaration. + * config/aarch64/aarch64.c (aarch64_regno_regclass): Handle new + stub registers class. + (aarch64_class_max_nregs): Likewise. + (aarch64_register_move_cost): Likewise. + (aarch64_sls_shared_thunks): Global array to store stub labels. + (aarch64_sls_emit_function_stub): New. + (aarch64_create_blr_label): New. + (aarch64_sls_emit_blr_function_thunks): New. + (aarch64_sls_emit_shared_blr_thunks): New. + (aarch64_asm_file_end): New. + (aarch64_indirect_call_asm): New. + (TARGET_ASM_FILE_END): Use aarch64_asm_file_end. + (TARGET_ASM_FUNCTION_EPILOGUE): Use + aarch64_sls_emit_blr_function_thunks. + * config/aarch64/aarch64.h (STB_REGNUM_P): New. + (enum reg_class): Add STUB_REGS class. + (machine_function): Introduce `call_via` array for + function-local stub labels. + * config/aarch64/aarch64.md (*call_insn, *call_value_insn): Use + aarch64_indirect_call_asm to emit code when hardening BLR + instructions. + * config/aarch64/constraints.md (Ucr): New constraint + representing registers for indirect calls. Is GENERAL_REGS + usually, and STUB_REGS when hardening BLR instruction against + SLS. + * config/aarch64/predicates.md (aarch64_general_reg): STUB_REGS class + is also a general register. + +2020-08-04 Matthew Malcomson + + * config/aarch64/aarch64-protos.h (aarch64_sls_barrier): New. + * config/aarch64/aarch64.c (aarch64_output_casesi): Emit + speculation barrier after BR instruction if needs be. + (aarch64_trampoline_init): Handle ptr_mode value & adjust size + of code copied. + (aarch64_sls_barrier): New. + (aarch64_asm_trampoline_template): Add needed barriers. + * config/aarch64/aarch64.h (AARCH64_ISA_SB): New. + (TARGET_SB): New. + (TRAMPOLINE_SIZE): Account for barrier. + * config/aarch64/aarch64.md (indirect_jump, *casesi_dispatch, + simple_return, *do_return, *sibcall_insn, *sibcall_value_insn): + Emit barrier if needs be, also account for possible barrier using + "sls_length" attribute. + (sls_length): New attribute. + (length): Determine default using any non-default sls_length + value. + +2020-08-04 Matthew Malcomson + + * config/aarch64/aarch64-protos.h (aarch64_harden_sls_retbr_p): + New. + (aarch64_harden_sls_blr_p): New. + * config/aarch64/aarch64.c (enum aarch64_sls_hardening_type): + New. + (aarch64_harden_sls_retbr_p): New. + (aarch64_harden_sls_blr_p): New. + (aarch64_validate_sls_mitigation): New. + (aarch64_override_options): Parse options for SLS mitigation. + * config/aarch64/aarch64.opt (-mharden-sls): New option. + * doc/invoke.texi: Document new option. + 2020-08-03 Jonathan Wakely Backported from master: diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f01da8770ae8..3a7230a5cf25 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200804 +20200805 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2fd9dfecbb9f..2142682e727c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2020-08-04 Matthew Malcomson + + * gcc.target/aarch64/sls-mitigation/sls-miti-blr-bti.c: New test. + * gcc.target/aarch64/sls-mitigation/sls-miti-blr.c: New test. + +2020-08-04 Matthew Malcomson + + * gcc.target/aarch64/sls-mitigation/sls-miti-retbr.c: New test. + * gcc.target/aarch64/sls-mitigation/sls-miti-retbr-pacret.c: + New test. + * gcc.target/aarch64/sls-mitigation/sls-mitigation.exp: New file. + * lib/target-supports.exp (check_effective_target_aarch64_asm_sb_ok): + New proc. + 2020-08-01 Iain Buclaw Backported from master: -- 2.47.2