From 0fca6d1ac50b809a75b8c354cd66e5b044b53179 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 14:41:45 +0800 Subject: [PATCH] RISC-V: Add vwsubu.v C++ API test gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwsubu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwsubu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_vx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C new file mode 100644 index 000000000000..4db7f81caee8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C new file mode 100644 index 000000000000..0567509af841 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C new file mode 100644 index 000000000000..a2474055ec93 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C new file mode 100644 index 000000000000..88d7d19d5e6e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C new file mode 100644 index 000000000000..7cd12165fe00 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C new file mode 100644 index 000000000000..df9b83e0f31b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C new file mode 100644 index 000000000000..c3aaa4bced63 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C new file mode 100644 index 000000000000..b643e35c5bf8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C new file mode 100644 index 000000000000..96a9d638369d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C new file mode 100644 index 000000000000..139cf2f50a10 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C new file mode 100644 index 000000000000..cfbc96ef38ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C new file mode 100644 index 000000000000..79f36d8c0f5f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C new file mode 100644 index 000000000000..b71a6e836084 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C new file mode 100644 index 000000000000..b3078fc640d7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C new file mode 100644 index 000000000000..f8af559aed92 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C new file mode 100644 index 000000000000..1b8dcca28643 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C new file mode 100644 index 000000000000..d6c4415f7639 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C new file mode 100644 index 000000000000..8abb5f24f571 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C new file mode 100644 index 000000000000..e6ea78ab3ec4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C new file mode 100644 index 000000000000..9529a30d3052 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C new file mode 100644 index 000000000000..030b4aeb4b4d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C new file mode 100644 index 000000000000..c83f7cfbfe01 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C new file mode 100644 index 000000000000..1945a356c40c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C new file mode 100644 index 000000000000..0a9c93bbdd10 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C new file mode 100644 index 000000000000..e76d4dbce583 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C new file mode 100644 index 000000000000..d9200e144369 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C new file mode 100644 index 000000000000..68bb7b46062d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C new file mode 100644 index 000000000000..4286106e6245 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C new file mode 100644 index 000000000000..4d87f64712b7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C new file mode 100644 index 000000000000..134696af1016 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.47.2