From 127770bcfccc21e7de214be9c54527a789ab790f Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 14 May 2025 22:07:47 -0400 Subject: [PATCH] drm/amdgpu: Revert retry based thrashing prevention on GFX 12.1.0 Revert the change to enable retry based thrashing prevention on GFX 12.1.0 for now as its causing data mismatch and slowness issues with multiple HIP tests. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 8f29a72353c71..522f478ca4bc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2512,17 +2512,6 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { uint32_t val; - /* Setup the TCP Thrashing control register */ - val = RREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL); - - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x0); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x0); - - WREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL, val); - /* Set the TCP UTCL0 register to enable atomics */ val = RREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1); val = REG_SET_FIELD(val, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); -- 2.47.3