From 1352f58d7c8dfb6ba0fbd2041bfc8b4b3966ec67 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 11 Dec 2025 14:48:19 +0800 Subject: [PATCH] dt-bindings: PCI: pci-imx6: Add external reference clock input i.MX95 PCIes have two reference clock inputs: one from internal PLL. It's wired inside chip and present as "ref" clock. It's not an optional clock. The other from off chip crystal oscillator. The "extref" clock refers to a reference clock from an external crystal oscillator through the CLKIN_N/P pair PADs. It is an optional clock, relied on the board design. Add additional optional external reference clock input for i.MX95 PCIes. Signed-off-by: Richard Zhu Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251211064821.2707001-3-hongxing.zhu@nxp.com --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index ca5f2970f217c..12a01f7a57443 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -44,7 +44,7 @@ properties: clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 interrupts: minItems: 1 @@ -212,14 +212,17 @@ allOf: then: properties: clocks: - maxItems: 5 + minItems: 5 + maxItems: 6 clock-names: + minItems: 5 items: - const: pcie - const: pcie_bus - const: pcie_phy - const: pcie_aux - const: ref + - const: extref # Optional unevaluatedProperties: false -- 2.47.3