From 14b6a73ce1a33e20d6e526415c0af34a9e01f64a Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 11 Dec 2025 12:46:52 +0800 Subject: [PATCH] drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.0 put wrong value into incorrect data into following function, which caused it to fail to match the correct item on smu v13.0.0: smu_cmn_print_pcie_levels() Fixes: a95f01edd80b ("drm/amd/pm: Use common helper for smuv13.0.0 dpm") Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index c95dbee06f49c..cddb8b283e3b6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -1234,8 +1234,10 @@ static int smu_v13_0_0_emit_clk_levels(struct smu_context *smu, return ret; pcie_table = &(dpm_context->dpm_tables.pcie_table); - return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, - lane_width, buf, offset); + return smu_cmn_print_pcie_levels(smu, pcie_table, + SMU_DPM_PCIE_GEN_IDX(gen_speed), + SMU_DPM_PCIE_WIDTH_IDX(lane_width), + buf, offset); case SMU_OD_SCLK: if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) -- 2.47.3