From 156f523f9582f1e6bcce27ece03f2776960408c8 Mon Sep 17 00:00:00 2001
From: Lili Cui <lili.cui@intel.com>
Date: Thu, 17 Nov 2022 15:50:46 +0800
Subject: [PATCH] x86: Enable 256 move by pieces for ALDERLAKE machine.

gcc/ChangeLog:

	* config/i386/x86-tune.def
	(X86_TUNE_AVX256_MOVE_BY_PIECES): Add alderlake.
	(X86_TUNE_AVX256_STORE_BY_PIECES): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pieces-memset-50.c: New test.
---
 gcc/config/i386/x86-tune.def                     |  4 ++--
 gcc/testsuite/gcc.target/i386/pieces-memset-50.c | 12 ++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-50.c

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 58e29e7806a5..cd66f3351137 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -536,12 +536,12 @@ DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512)
 /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
    AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
-	  m_CORE_AVX512)
+	  m_ALDERLAKE | m_CORE_AVX2)
 
 /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
    AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
-	  m_CORE_AVX512)
+	  m_ALDERLAKE | m_CORE_AVX2)
 
 /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
    AVX instructions.  */
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-50.c b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
new file mode 100644
index 000000000000..c09e7c3649c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=alderlake" } */
+
+extern char *dst;
+
+void
+foo (int x)
+{
+  __builtin_memset (dst, x, 64);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
-- 
2.47.2