From 18649ffbb63bca40896f973b6997914f9d603b1e Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:58 +0800 Subject: [PATCH] riscv: dts: anlogic: dr1v90: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi index a5d0765ade323..9fe183f5f5c8d 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ mmu-type = "riscv,sv39"; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; cpu0_intc: interrupt-controller { -- 2.47.3