From 1a0d48060d6b0b7783adabb321f0a96ead16080b Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Tue, 26 Nov 2024 13:05:00 -0800 Subject: [PATCH] aarch64: Fix fp8_scalar_1.c's stacktest1 The function body test was expecting: umov w0, v0.b[0] strb w0, [sp, 15] But the code generation was improved after r15-5375-gbeec291225be to just: str b0, [sp, 15] which is correct and better because no longer need to move between SIMD registers and the GPRs. This changes the function body test to new better code generation. Pushed as obvious after a test of the testcase to make sure it now passes. gcc/testsuite/ChangeLog: * gcc.target/aarch64/fp8_scalar_1.c (stacktest1): Fix for new improved code generation. Signed-off-by: Andrew Pinski --- gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c index 61edf06401b8..6632c77e0c63 100644 --- a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c @@ -7,9 +7,8 @@ /* **stacktest1: -** umov w0, v0.b\[0\] ** sub sp, sp, #16 -** strb w0, \[sp, 15\] +** str b0, \[sp, 15\] ** ldr b0, \[sp, 15\] ** add sp, sp, 16 ** ret -- 2.47.2