From 1cb0958a26aeffe315a60b3cbbc56b94246cc25a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:57 +0200 Subject: [PATCH] arm64: dts: rockchip: Correctly describe the ethernet phy on rk3368-lion So far, the board used the phy implicitly using the deprecated snps reset properties. Improve that and describe the PHY correctly under the new mdio node. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 8ccc3184a8362..61c52bd91784f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -154,13 +154,11 @@ assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; clock_in_out = "input"; + phy-handle = <&vsc8531_2>; phy-supply = <&vcc33_io>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; @@ -285,7 +283,25 @@ status = "okay"; }; +&mdio { + vsc8531_2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { + ethernet { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pins: module-led-pins { rockchip,pins = -- 2.47.3