From 1e6324f7f36fc3850032b13577b2473a6a3d64bf Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Fri, 3 Feb 2023 15:45:23 +0800 Subject: [PATCH] RISC-V: Add vadd.vx C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vadd_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_rv32-1.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv32-2.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv32-3.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-1.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-2.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-3.C | 292 +++++++++ 30 files changed, 10422 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C new file mode 100644 index 000000000000..24c5d51a2897 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C new file mode 100644 index 000000000000..7f296881f5ea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C new file mode 100644 index 000000000000..f56c55a21545 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C new file mode 100644 index 000000000000..973751af9b83 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C new file mode 100644 index 000000000000..23e5a4604ec1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C new file mode 100644 index 000000000000..d9addcc16760 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C new file mode 100644 index 000000000000..486d80fd2e41 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C new file mode 100644 index 000000000000..57df9c7b74e7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C new file mode 100644 index 000000000000..5b3fc3da4f54 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C new file mode 100644 index 000000000000..0d52c4ac0a4b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C new file mode 100644 index 000000000000..cbed2852b820 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C new file mode 100644 index 000000000000..a1f5e5904436 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C new file mode 100644 index 000000000000..95c078f37981 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C new file mode 100644 index 000000000000..fb3e812499af --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C new file mode 100644 index 000000000000..44aed96a6c90 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C new file mode 100644 index 000000000000..9d525139ed87 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C new file mode 100644 index 000000000000..0eaab87d5470 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C new file mode 100644 index 000000000000..d933b7fdeb9d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C new file mode 100644 index 000000000000..4f43005659e9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C new file mode 100644 index 000000000000..3af29aaaef13 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C new file mode 100644 index 000000000000..db3f0f10cde3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C new file mode 100644 index 000000000000..3b3377f34580 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C new file mode 100644 index 000000000000..ece9f1a14fc1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C new file mode 100644 index 000000000000..56f7c5d56124 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C new file mode 100644 index 000000000000..91b816f125de --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C new file mode 100644 index 000000000000..65655949df64 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C new file mode 100644 index 000000000000..8013027670d3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C new file mode 100644 index 000000000000..e33ae90a3c6a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C new file mode 100644 index 000000000000..560b9d355f59 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C new file mode 100644 index 000000000000..2ff074ac4093 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ -- 2.47.2