From 1fa7dde8d680f28ed66db47309ed5e8f2789054d Mon Sep 17 00:00:00 2001
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Fri, 10 Nov 2023 07:33:25 +0800
Subject: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec
 pattern

Since cond_copysign has been support into match.pd (middle-end).
We don't need to support conditional copysign by RTL combine pass.

Instead, we can support it by direct explicit cond_copysign optab.

conditional copysign tests are already available in the testsuite.
No need to add tests.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*cond_copysign<mode>): Remove.
	* config/riscv/autovec.md (cond_copysign<mode>): New pattern.
---
 gcc/config/riscv/autovec-opt.md | 22 ----------------------
 gcc/config/riscv/autovec.md     | 22 ++++++++++++++++++++++
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 3c87e66ea491..986ac6e91810 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -486,28 +486,6 @@
 }
 [(set_attr "type" "vector")])
 
-;; Combine vfsgnj.vv + vcond_mask
-(define_insn_and_split "*cond_copysign<mode>"
-   [(set (match_operand:V_VLSF 0 "register_operand")
-    (if_then_else:V_VLSF
-      (match_operand:<VM> 1 "register_operand")
-      (unspec:V_VLSF
-       [(match_operand:V_VLSF 2 "register_operand")
-        (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN)
-      (match_operand:V_VLSF 4 "register_operand")))]
-   "TARGET_VECTOR && can_create_pseudo_p ()"
-   "#"
-   "&& 1"
-   [(const_int 0)]
-{
-  insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode);
-  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
-               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
-  riscv_vector::expand_cond_len_binop (icode, ops);
-   DONE;
-}
-[(set_attr "type" "vector")])
-
 ;; Combine vnsra + vcond_mask
 (define_insn_and_split "*cond_v<any_shiftrt:optab><any_extend:optab>trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 973dc4ac2352..33722ea1139e 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1808,6 +1808,28 @@
   DONE;
 })
 
+;; -------------------------------------------------------------------------
+;; ---- [FP] Conditional copysign operations
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfsgnj
+;; -------------------------------------------------------------------------
+
+(define_expand "cond_copysign<mode>"
+  [(match_operand:V_VLSF 0 "register_operand")
+   (match_operand:<VM> 1 "register_operand")
+   (match_operand:V_VLSF 2 "register_operand")
+   (match_operand:V_VLSF 3 "register_operand")
+   (match_operand:V_VLSF 4 "register_operand")]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_binop (icode, ops);
+  DONE;
+})
+
 ;; -------------------------------------------------------------------------
 ;; ---- [INT] Conditional ternary operations
 ;; -------------------------------------------------------------------------
-- 
2.47.2