From 2095a9d538e0ea00f684fea4e55deaff21bd4a1b Mon Sep 17 00:00:00 2001 From: Monk Chiang Date: Sat, 7 Apr 2018 04:24:48 +0000 Subject: [PATCH] [NDS32] Add more intrinsic register names. gcc/ * config/nds32/nds32.c (nds32_intrinsic_register_names): Add more intrinsic register names. * config/nds32/nds32_intrinsic.h (nds32_intrinsic_registers): Add more intrinsic register enum values and macros. From-SVN: r259202 --- gcc/ChangeLog | 7 + gcc/config/nds32/nds32.c | 155 +++++++++++++- gcc/config/nds32/nds32_intrinsic.h | 315 ++++++++++++++++++++++++++++- 3 files changed, 474 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6c631cd59c1..260baebd2a81 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-04-07 Monk Chiang + + * config/nds32/nds32.c (nds32_intrinsic_register_names): Add more + intrinsic register names. + * config/nds32/nds32_intrinsic.h (nds32_intrinsic_registers): Add more + intrinsic register enum values and macros. + 2018-04-07 Chung-Ju Wu * config/nds32/nds32.c (nds32_legitimate_index_p): Modify condition diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index b4c31a4a90f5..2b52d8409bc1 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -81,7 +81,160 @@ NOTE that the base value starting from 1024. */ static const char * const nds32_intrinsic_register_names[] = { - "$PSW", "$IPSW", "$ITYPE", "$IPC" + "$CPU_VER", + "$ICM_CFG", + "$DCM_CFG", + "$MMU_CFG", + "$MSC_CFG", + "$MSC_CFG2", + "$CORE_ID", + "$FUCOP_EXIST", + + "$PSW", + "$IPSW", + "$P_IPSW", + "$IVB", + "$EVA", + "$P_EVA", + "$ITYPE", + "$P_ITYPE", + + "$MERR", + "$IPC", + "$P_IPC", + "$OIPC", + "$P_P0", + "$P_P1", + + "$INT_MASK", + "$INT_MASK2", + "$INT_MASK3", + "$INT_PEND", + "$INT_PEND2", + "$INT_PEND3", + "$SP_USR", + "$SP_PRIV", + "$INT_PRI", + "$INT_PRI2", + "$INT_PRI3", + "$INT_PRI4", + "$INT_CTRL", + "$INT_TRIGGER", + "$INT_TRIGGER2", + "$INT_GPR_PUSH_DIS", + + "$MMU_CTL", + "$L1_PPTB", + "$TLB_VPN", + "$TLB_DATA", + "$TLB_MISC", + "$VLPT_IDX", + "$ILMB", + "$DLMB", + + "$CACHE_CTL", + "$HSMP_SADDR", + "$HSMP_EADDR", + "$SDZ_CTL", + "$N12MISC_CTL", + "$MISC_CTL", + "$ECC_MISC", + + "$BPC0", + "$BPC1", + "$BPC2", + "$BPC3", + "$BPC4", + "$BPC5", + "$BPC6", + "$BPC7", + + "$BPA0", + "$BPA1", + "$BPA2", + "$BPA3", + "$BPA4", + "$BPA5", + "$BPA6", + "$BPA7", + + "$BPAM0", + "$BPAM1", + "$BPAM2", + "$BPAM3", + "$BPAM4", + "$BPAM5", + "$BPAM6", + "$BPAM7", + + "$BPV0", + "$BPV1", + "$BPV2", + "$BPV3", + "$BPV4", + "$BPV5", + "$BPV6", + "$BPV7", + + "$BPCID0", + "$BPCID1", + "$BPCID2", + "$BPCID3", + "$BPCID4", + "$BPCID5", + "$BPCID6", + "$BPCID7", + + "$EDM_CFG", + "$EDMSW", + "$EDM_CTL", + "$EDM_DTR", + "$BPMTC", + "$DIMBR", + + "$TECR0", + "$TECR1", + "$PFMC0", + "$PFMC1", + "$PFMC2", + "$PFM_CTL", + "$PFT_CTL", + "$HSP_CTL", + "$SP_BOUND", + "$SP_BOUND_PRIV", + "$SP_BASE", + "$SP_BASE_PRIV", + "$FUCOP_CTL", + "$PRUSR_ACC_CTL", + + "$DMA_CFG", + "$DMA_GCSW", + "$DMA_CHNSEL", + "$DMA_ACT", + "$DMA_SETUP", + "$DMA_ISADDR", + "$DMA_ESADDR", + "$DMA_TCNT", + "$DMA_STATUS", + "$DMA_2DSET", + "$DMA_2DSCTL", + "$DMA_RCNT", + "$DMA_HSTATUS", + + "$PC", + "$SP_USR1", + "$SP_USR2", + "$SP_USR3", + "$SP_PRIV1", + "$SP_PRIV2", + "$SP_PRIV3", + "$BG_REGION", + "$SFCR", + "$SIGN", + "$ISIGN", + "$P_ISIGN", + "$IFC_LP", + "$ITB" }; diff --git a/gcc/config/nds32/nds32_intrinsic.h b/gcc/config/nds32/nds32_intrinsic.h index cebc9a5d057a..5656ce5a07d4 100644 --- a/gcc/config/nds32/nds32_intrinsic.h +++ b/gcc/config/nds32/nds32_intrinsic.h @@ -26,12 +26,323 @@ #ifndef _NDS32_INTRINSIC_H #define _NDS32_INTRINSIC_H +/* General instrinsic register names. */ enum nds32_intrinsic_registers { - __NDS32_REG_PSW__ = 1024, + __NDS32_REG_CPU_VER__ = 1024, + __NDS32_REG_ICM_CFG__, + __NDS32_REG_DCM_CFG__, + __NDS32_REG_MMU_CFG__, + __NDS32_REG_MSC_CFG__, + __NDS32_REG_MSC_CFG2__, + __NDS32_REG_CORE_ID__, + __NDS32_REG_FUCOP_EXIST__, + + __NDS32_REG_PSW__, __NDS32_REG_IPSW__, + __NDS32_REG_P_IPSW__, + __NDS32_REG_IVB__, + __NDS32_REG_EVA__, + __NDS32_REG_P_EVA__, __NDS32_REG_ITYPE__, - __NDS32_REG_IPC__ + __NDS32_REG_P_ITYPE__, + + __NDS32_REG_MERR__, + __NDS32_REG_IPC__, + __NDS32_REG_P_IPC__, + __NDS32_REG_OIPC__, + __NDS32_REG_P_P0__, + __NDS32_REG_P_P1__, + + __NDS32_REG_INT_MASK__, + __NDS32_REG_INT_MASK2__, + __NDS32_REG_INT_MASK3__, + __NDS32_REG_INT_PEND__, + __NDS32_REG_INT_PEND2__, + __NDS32_REG_INT_PEND3__, + __NDS32_REG_SP_USR__, + __NDS32_REG_SP_PRIV__, + __NDS32_REG_INT_PRI__, + __NDS32_REG_INT_PRI2__, + __NDS32_REG_INT_PRI3__, + __NDS32_REG_INT_PRI4__, + __NDS32_REG_INT_CTRL__, + __NDS32_REG_INT_TRIGGER__, + __NDS32_REG_INT_TRIGGER2__, + __NDS32_REG_INT_GPR_PUSH_DIS__, + + __NDS32_REG_MMU_CTL__, + __NDS32_REG_L1_PPTB__, + __NDS32_REG_TLB_VPN__, + __NDS32_REG_TLB_DATA__, + __NDS32_REG_TLB_MISC__, + __NDS32_REG_VLPT_IDX__, + __NDS32_REG_ILMB__, + __NDS32_REG_DLMB__, + + __NDS32_REG_CACHE_CTL__, + __NDS32_REG_HSMP_SADDR__, + __NDS32_REG_HSMP_EADDR__, + __NDS32_REG_SDZ_CTL__, + __NDS32_REG_N12MISC_CTL__, + __NDS32_REG_MISC_CTL__, + __NDS32_REG_ECC_MISC__, + + __NDS32_REG_BPC0__, + __NDS32_REG_BPC1__, + __NDS32_REG_BPC2__, + __NDS32_REG_BPC3__, + __NDS32_REG_BPC4__, + __NDS32_REG_BPC5__, + __NDS32_REG_BPC6__, + __NDS32_REG_BPC7__, + + __NDS32_REG_BPA0__, + __NDS32_REG_BPA1__, + __NDS32_REG_BPA2__, + __NDS32_REG_BPA3__, + __NDS32_REG_BPA4__, + __NDS32_REG_BPA5__, + __NDS32_REG_BPA6__, + __NDS32_REG_BPA7__, + + __NDS32_REG_BPAM0__, + __NDS32_REG_BPAM1__, + __NDS32_REG_BPAM2__, + __NDS32_REG_BPAM3__, + __NDS32_REG_BPAM4__, + __NDS32_REG_BPAM5__, + __NDS32_REG_BPAM6__, + __NDS32_REG_BPAM7__, + + __NDS32_REG_BPV0__, + __NDS32_REG_BPV1__, + __NDS32_REG_BPV2__, + __NDS32_REG_BPV3__, + __NDS32_REG_BPV4__, + __NDS32_REG_BPV5__, + __NDS32_REG_BPV6__, + __NDS32_REG_BPV7__, + + __NDS32_REG_BPCID0__, + __NDS32_REG_BPCID1__, + __NDS32_REG_BPCID2__, + __NDS32_REG_BPCID3__, + __NDS32_REG_BPCID4__, + __NDS32_REG_BPCID5__, + __NDS32_REG_BPCID6__, + __NDS32_REG_BPCID7__, + + __NDS32_REG_EDM_CFG__, + __NDS32_REG_EDMSW__, + __NDS32_REG_EDM_CTL__, + __NDS32_REG_EDM_DTR__, + __NDS32_REG_BPMTC__, + __NDS32_REG_DIMBR__, + + __NDS32_REG_TECR0__, + __NDS32_REG_TECR1__, + __NDS32_REG_PFMC0__, + __NDS32_REG_PFMC1__, + __NDS32_REG_PFMC2__, + __NDS32_REG_PFM_CTL__, + __NDS32_REG_PFT_CTL__, + __NDS32_REG_HSP_CTL__, + __NDS32_REG_SP_BOUND__, + __NDS32_REG_SP_BOUND_PRIV__, + __NDS32_REG_SP_BASE__, + __NDS32_REG_SP_BASE_PRIV__, + __NDS32_REG_FUCOP_CTL__, + __NDS32_REG_PRUSR_ACC_CTL__, + + __NDS32_REG_DMA_CFG__, + __NDS32_REG_DMA_GCSW__, + __NDS32_REG_DMA_CHNSEL__, + __NDS32_REG_DMA_ACT__, + __NDS32_REG_DMA_SETUP__, + __NDS32_REG_DMA_ISADDR__, + __NDS32_REG_DMA_ESADDR__, + __NDS32_REG_DMA_TCNT__, + __NDS32_REG_DMA_STATUS__, + __NDS32_REG_DMA_2DSET__, + __NDS32_REG_DMA_2DSCTL__, + __NDS32_REG_DMA_RCNT__, + __NDS32_REG_DMA_HSTATUS__, + + __NDS32_REG_PC__, + __NDS32_REG_SP_USR1__, + __NDS32_REG_SP_USR2__, + __NDS32_REG_SP_USR3__, + __NDS32_REG_SP_PRIV1__, + __NDS32_REG_SP_PRIV2__, + __NDS32_REG_SP_PRIV3__, + __NDS32_REG_BG_REGION__, + __NDS32_REG_SFCR__, + __NDS32_REG_SIGN__, + __NDS32_REG_ISIGN__, + __NDS32_REG_P_ISIGN__, + __NDS32_REG_IFC_LP__, + __NDS32_REG_ITB__ }; + +/* ------------------------------------------------------------------------ */ + +/* Define intrinsic register name macro for compatibility. */ +#define NDS32_SR_CPU_VER __NDS32_REG_CPU_VER__ +#define NDS32_SR_ICM_CFG __NDS32_REG_ICM_CFG__ +#define NDS32_SR_DCM_CFG __NDS32_REG_DCM_CFG__ +#define NDS32_SR_MMU_CFG __NDS32_REG_MMU_CFG__ +#define NDS32_SR_MSC_CFG __NDS32_REG_MSC_CFG__ +#define NDS32_SR_MSC_CFG2 __NDS32_REG_MSC_CFG2__ +#define NDS32_SR_CORE_ID __NDS32_REG_CORE_ID__ +#define NDS32_SR_FUCOP_EXIST __NDS32_REG_FUCOP_EXIST__ +#define NDS32_SR_PSW __NDS32_REG_PSW__ +#define NDS32_SR_IPSW __NDS32_REG_IPSW__ +#define NDS32_SR_P_IPSW __NDS32_REG_P_IPSW__ +#define NDS32_SR_IVB __NDS32_REG_IVB__ +#define NDS32_SR_EVA __NDS32_REG_EVA__ +#define NDS32_SR_P_EVA __NDS32_REG_P_EVA__ +#define NDS32_SR_ITYPE __NDS32_REG_ITYPE__ +#define NDS32_SR_P_ITYPE __NDS32_REG_P_ITYPE__ +#define NDS32_SR_MERR __NDS32_REG_MERR__ +#define NDS32_SR_IPC __NDS32_REG_IPC__ +#define NDS32_SR_P_IPC __NDS32_REG_P_IPC__ +#define NDS32_SR_OIPC __NDS32_REG_OIPC__ +#define NDS32_SR_P_P0 __NDS32_REG_P_P0__ +#define NDS32_SR_P_P1 __NDS32_REG_P_P1__ +#define NDS32_SR_INT_MASK __NDS32_REG_INT_MASK__ +#define NDS32_SR_INT_MASK2 __NDS32_REG_INT_MASK2__ +#define NDS32_SR_INT_MASK3 __NDS32_REG_INT_MASK3__ +#define NDS32_SR_INT_PEND __NDS32_REG_INT_PEND__ +#define NDS32_SR_INT_PEND2 __NDS32_REG_INT_PEND2__ +#define NDS32_SR_INT_PEND3 __NDS32_REG_INT_PEND3__ +#define NDS32_SR_SP_USR __NDS32_REG_SP_USR__ +#define NDS32_SR_SP_PRIV __NDS32_REG_SP_PRIV__ +#define NDS32_SR_INT_PRI __NDS32_REG_INT_PRI__ +#define NDS32_SR_INT_PRI2 __NDS32_REG_INT_PRI2__ +#define NDS32_SR_INT_PRI3 __NDS32_REG_INT_PRI3__ +#define NDS32_SR_INT_PRI4 __NDS32_REG_INT_PRI4__ +#define NDS32_SR_INT_CTRL __NDS32_REG_INT_CTRL__ +#define NDS32_SR_INT_TRIGGER __NDS32_REG_INT_TRIGGER__ +#define NDS32_SR_INT_TRIGGER2 __NDS32_REG_INT_TRIGGER2__ +#define NDS32_SR_INT_GPR_PUSH_DIS __NDS32_REG_INT_GPR_PUSH_DIS__ +#define NDS32_SR_MMU_CTL __NDS32_REG_MMU_CTL__ +#define NDS32_SR_L1_PPTB __NDS32_REG_L1_PPTB__ +#define NDS32_SR_TLB_VPN __NDS32_REG_TLB_VPN__ +#define NDS32_SR_TLB_DATA __NDS32_REG_TLB_DATA__ +#define NDS32_SR_TLB_MISC __NDS32_REG_TLB_MISC__ +#define NDS32_SR_VLPT_IDX __NDS32_REG_VLPT_IDX__ +#define NDS32_SR_ILMB __NDS32_REG_ILMB__ +#define NDS32_SR_DLMB __NDS32_REG_DLMB__ +#define NDS32_SR_CACHE_CTL __NDS32_REG_CACHE_CTL__ +#define NDS32_SR_HSMP_SADDR __NDS32_REG_HSMP_SADDR__ +#define NDS32_SR_HSMP_EADDR __NDS32_REG_HSMP_EADDR__ +#define NDS32_SR_SDZ_CTL __NDS32_REG_SDZ_CTL__ +#define NDS32_SR_N12MISC_CTL __NDS32_REG_N12MISC_CTL__ +#define NDS32_SR_MISC_CTL __NDS32_REG_MISC_CTL__ +#define NDS32_SR_ECC_MISC __NDS32_REG_ECC_MISC__ +#define NDS32_SR_BPC0 __NDS32_REG_BPC0__ +#define NDS32_SR_BPC1 __NDS32_REG_BPC1__ +#define NDS32_SR_BPC2 __NDS32_REG_BPC2__ +#define NDS32_SR_BPC3 __NDS32_REG_BPC3__ +#define NDS32_SR_BPC4 __NDS32_REG_BPC4__ +#define NDS32_SR_BPC5 __NDS32_REG_BPC5__ +#define NDS32_SR_BPC6 __NDS32_REG_BPC6__ +#define NDS32_SR_BPC7 __NDS32_REG_BPC7__ +#define NDS32_SR_BPA0 __NDS32_REG_BPA0__ +#define NDS32_SR_BPA1 __NDS32_REG_BPA1__ +#define NDS32_SR_BPA2 __NDS32_REG_BPA2__ +#define NDS32_SR_BPA3 __NDS32_REG_BPA3__ +#define NDS32_SR_BPA4 __NDS32_REG_BPA4__ +#define NDS32_SR_BPA5 __NDS32_REG_BPA5__ +#define NDS32_SR_BPA6 __NDS32_REG_BPA6__ +#define NDS32_SR_BPA7 __NDS32_REG_BPA7__ +#define NDS32_SR_BPAM0 __NDS32_REG_BPAM0__ +#define NDS32_SR_BPAM1 __NDS32_REG_BPAM1__ +#define NDS32_SR_BPAM2 __NDS32_REG_BPAM2__ +#define NDS32_SR_BPAM3 __NDS32_REG_BPAM3__ +#define NDS32_SR_BPAM4 __NDS32_REG_BPAM4__ +#define NDS32_SR_BPAM5 __NDS32_REG_BPAM5__ +#define NDS32_SR_BPAM6 __NDS32_REG_BPAM6__ +#define NDS32_SR_BPAM7 __NDS32_REG_BPAM7__ +#define NDS32_SR_BPV0 __NDS32_REG_BPV0__ +#define NDS32_SR_BPV1 __NDS32_REG_BPV1__ +#define NDS32_SR_BPV2 __NDS32_REG_BPV2__ +#define NDS32_SR_BPV3 __NDS32_REG_BPV3__ +#define NDS32_SR_BPV4 __NDS32_REG_BPV4__ +#define NDS32_SR_BPV5 __NDS32_REG_BPV5__ +#define NDS32_SR_BPV6 __NDS32_REG_BPV6__ +#define NDS32_SR_BPV7 __NDS32_REG_BPV7__ +#define NDS32_SR_BPCID0 __NDS32_REG_BPCID0__ +#define NDS32_SR_BPCID1 __NDS32_REG_BPCID1__ +#define NDS32_SR_BPCID2 __NDS32_REG_BPCID2__ +#define NDS32_SR_BPCID3 __NDS32_REG_BPCID3__ +#define NDS32_SR_BPCID4 __NDS32_REG_BPCID4__ +#define NDS32_SR_BPCID5 __NDS32_REG_BPCID5__ +#define NDS32_SR_BPCID6 __NDS32_REG_BPCID6__ +#define NDS32_SR_BPCID7 __NDS32_REG_BPCID7__ +#define NDS32_SR_EDM_CFG __NDS32_REG_EDM_CFG__ +#define NDS32_SR_EDMSW __NDS32_REG_EDMSW__ +#define NDS32_SR_EDM_CTL __NDS32_REG_EDM_CTL__ +#define NDS32_SR_EDM_DTR __NDS32_REG_EDM_DTR__ +#define NDS32_SR_BPMTC __NDS32_REG_BPMTC__ +#define NDS32_SR_DIMBR __NDS32_REG_DIMBR__ +#define NDS32_SR_TECR0 __NDS32_REG_TECR0__ +#define NDS32_SR_TECR1 __NDS32_REG_TECR1__ +#define NDS32_SR_PFMC0 __NDS32_REG_PFMC0__ +#define NDS32_SR_PFMC1 __NDS32_REG_PFMC1__ +#define NDS32_SR_PFMC2 __NDS32_REG_PFMC2__ +#define NDS32_SR_PFM_CTL __NDS32_REG_PFM_CTL__ +#define NDS32_SR_HSP_CTL __NDS32_REG_HSP_CTL__ +#define NDS32_SR_SP_BOUND __NDS32_REG_SP_BOUND__ +#define NDS32_SR_SP_BOUND_PRIV __NDS32_REG_SP_BOUND_PRIV__ +#define NDS32_SR_SP_BASE __NDS32_REG_SP_BASE__ +#define NDS32_SR_SP_BASE_PRIV __NDS32_REG_SP_BASE_PRIV__ +#define NDS32_SR_FUCOP_CTL __NDS32_REG_FUCOP_CTL__ +#define NDS32_SR_PRUSR_ACC_CTL __NDS32_REG_PRUSR_ACC_CTL__ +#define NDS32_SR_DMA_CFG __NDS32_REG_DMA_CFG__ +#define NDS32_SR_DMA_GCSW __NDS32_REG_DMA_GCSW__ +#define NDS32_SR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__ +#define NDS32_SR_DMA_ACT __NDS32_REG_DMA_ACT__ +#define NDS32_SR_DMA_SETUP __NDS32_REG_DMA_SETUP__ +#define NDS32_SR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__ +#define NDS32_SR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__ +#define NDS32_SR_DMA_TCNT __NDS32_REG_DMA_TCNT__ +#define NDS32_SR_DMA_STATUS __NDS32_REG_DMA_STATUS__ +#define NDS32_SR_DMA_2DSET __NDS32_REG_DMA_2DSET__ +#define NDS32_SR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__ +#define NDS32_SR_DMA_RCNT __NDS32_REG_DMA_RCNT__ +#define NDS32_SR_DMA_HSTATUS __NDS32_REG_DMA_HSTATUS__ +#define NDS32_SR_SP_USR1 __NDS32_REG_SP_USR1__ +#define NDS32_SR_SP_USR2 __NDS32_REG_SP_USR2__ +#define NDS32_SR_SP_USR3 __NDS32_REG_SP_USR3__ +#define NDS32_SR_SP_PRIV1 __NDS32_REG_SP_PRIV1__ +#define NDS32_SR_SP_PRIV2 __NDS32_REG_SP_PRIV2__ +#define NDS32_SR_SP_PRIV3 __NDS32_REG_SP_PRIV3__ +#define NDS32_SR_BG_REGION __NDS32_REG_BG_REGION__ +#define NDS32_SR_SFCR __NDS32_REG_SFCR__ +#define NDS32_SR_SIGN __NDS32_REG_SIGN__ +#define NDS32_SR_ISIGN __NDS32_REG_ISIGN__ +#define NDS32_SR_P_ISIGN __NDS32_REG_P_ISIGN__ + +#define NDS32_USR_PC __NDS32_REG_PC__ +#define NDS32_USR_DMA_CFG __NDS32_REG_DMA_CFG__ +#define NDS32_USR_DMA_GCSW __NDS32_REG_DMA_GCSW__ +#define NDS32_USR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__ +#define NDS32_USR_DMA_ACT __NDS32_REG_DMA_ACT__ +#define NDS32_USR_DMA_SETUP __NDS32_REG_DMA_SETUP__ +#define NDS32_USR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__ +#define NDS32_USR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__ +#define NDS32_USR_DMA_TCNT __NDS32_REG_DMA_TCNT__ +#define NDS32_USR_DMA_STATUS __NDS32_REG_DMA_STATUS__ +#define NDS32_USR_DMA_2DSET __NDS32_REG_DMA_2DSET__ +#define NDS32_USR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__ +#define NDS32_USR_PFMC0 __NDS32_REG_PFMC0__ +#define NDS32_USR_PFMC1 __NDS32_REG_PFMC1__ +#define NDS32_USR_PFMC2 __NDS32_REG_PFMC2__ +#define NDS32_USR_PFM_CTL __NDS32_REG_PFM_CTL__ +#define NDS32_USR_IFC_LP __NDS32_REG_IFC_LP__ +#define NDS32_USR_ITB __NDS32_REG_ITB__ + #endif /* nds32_intrinsic.h */ -- 2.47.2