From 20b02acbd89e4fc883670a7f7f517fc0a11bb5f7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 7 Jun 2025 21:44:39 +0200 Subject: [PATCH] arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock The Sparrow Hawk board supplies the PCIe controller input clock and PCIe bus clock from separate outputs of the Renesas 9FGV0441 clock generator. Describe this split bus configuration in the board DT. The topology looks as follows: ____________ _____________ | R-Car PCIe | | PCIe device | | | | | | PCIe RX<|==================|>PCIe TX | | PCIe TX<|==================|>PCIe RX | | | | | | PCIe CLK<|======.. ..======|>PCIe CLK | '------------' || || '-------------' || || ____________ || || | 9FGV0441 | || || | | || || | CLK DIF0<|======'' || | CLK DIF1<|=========='' | CLK DIF2<| | CLK DIF3<| '------------' Acked-by: Manivannan Sadhasivam Reviewed-by: Geert Uytterhoeven Signed-off-by: Marek Vasut Link: https://lore.kernel.org/20250607194541.79176-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779g3-sparrow-hawk.dts | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index b8698e07add56..9ba23129e65ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -130,6 +130,13 @@ }; }; + /* Page 26 / PCIe.0/1 CLK */ + pcie_refclk: clk-x8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + reg_1p2v: regulator-1p2v { compatible = "regulator-fixed"; regulator-name = "fixed-1.2V"; @@ -404,6 +411,14 @@ reg = <2>; #address-cells = <1>; #size-cells = <0>; + + /* Page 26 / PCIe.0/1 CLK */ + pcie_clk: clk@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&pcie_refclk>; + #clock-cells = <1>; + }; }; i2c0_mux3: i2c@3 { @@ -487,26 +502,38 @@ /* Page 26 / 2230 Key M M.2 */ &pcie0_clkref { - clock-frequency = <100000000>; + status = "disabled"; }; &pciec0 { + clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>; reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pciec0_rp { + clocks = <&pcie_clk 1>; + vpcie3v3-supply = <®_3p3v>; +}; + /* Page 25 / PCIe to USB */ &pcie1_clkref { - clock-frequency = <100000000>; + status = "disabled"; }; &pciec1 { + clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>; /* uPD720201 is PCIe Gen2 x1 device */ num-lanes = <1>; reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pciec1_rp { + clocks = <&pcie_clk 3>; + vpcie3v3-supply = <®_3p3v>; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; -- 2.47.2