From 260aef187f7ffaf03a1f4c51b5b748f1ca026696 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 15 Dec 2025 21:23:51 +0200 Subject: [PATCH] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST stream BW A DSC compressed stream requires FEC (except for eDP), which has a BW overhead on non-UHBR links that must be accounted for explicitly. Do that during computing the required BW. Note that the overhead doesn't need to be accounted for on UHBR links where FEC is always enabled and so the corresponding overhead is part of the channel coding efficiency instead (i.e. the overhead is part of the available vs. the required BW). Reviewed-by: Luca Coelho Signed-off-by: Imre Deak Link: https://patch.msgid.link/20251215192357.172201-12-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a2939843a72ad..dc14349de3941 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2086,12 +2086,16 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, if (ret) continue; } else { + unsigned long bw_overhead_flags = + pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; + if (!is_bw_sufficient_for_dsc_config(intel_dp, link_rate, lane_count, adjusted_mode->crtc_clock, adjusted_mode->hdisplay, pipe_config->dsc.slice_count, - dsc_bpp_x16, 0)) + dsc_bpp_x16, + bw_overhead_flags)) continue; } -- 2.47.3