From 26d6e02c42bdf7bef0cf1166fedd740df982b871 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 13 Feb 2023 21:12:25 +0000 Subject: [PATCH] arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq Factorize vmaxnmaq and vminnmaq so that they use the same pattern. 2022-09-08 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ) (MVE_VMAXNMA_VMINNMAQ_M): New. (mve_insn): Add vmaxnma, vminnma. * config/arm/mve.md (mve_vmaxnmaq_f, mve_vminnmaq_f): Merge into ... (@mve_q_f): ... this. (mve_vmaxnmaq_m_f, mve_vminnmaq_m_f): Merge into ... (@mve_q_m_f): ... this. --- gcc/config/arm/iterators.md | 14 +++++++++++ gcc/config/arm/mve.md | 49 ++++++++----------------------------- 2 files changed, 24 insertions(+), 39 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 26ad687cefd6..8edbf5a55cf8 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -611,6 +611,16 @@ VMINNMVQ_P_F ]) +(define_int_iterator MVE_VMAXNMA_VMINNMAQ [ + VMAXNMAQ_F + VMINNMAQ_F + ]) + +(define_int_iterator MVE_VMAXNMA_VMINNMAQ_M [ + VMAXNMAQ_M_F + VMINNMAQ_M_F + ]) + (define_int_iterator MVE_MOVN [ VMOVNBQ_S VMOVNBQ_U VMOVNTQ_S VMOVNTQ_U @@ -662,6 +672,8 @@ (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub") (VMAXAVQ_P_S "vmaxav") (VMAXAVQ_S "vmaxav") + (VMAXNMAQ_F "vmaxnma") + (VMAXNMAQ_M_F "vmaxnma") (VMAXNMAVQ_F "vmaxnmav") (VMAXNMAVQ_P_F "vmaxnmav") (VMAXNMQ_M_F "vmaxnm") @@ -672,6 +684,8 @@ (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv") (VMINAVQ_P_S "vminav") (VMINAVQ_S "vminav") + (VMINNMAQ_F "vminnma") + (VMINNMAQ_M_F "vminnma") (VMINNMAVQ_F "vminnmav") (VMINNMAVQ_P_F "vminnmav") (VMINNMQ_M_F "vminnm") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 2aebaa99bbf1..ef0b6fd3dedf 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1425,17 +1425,18 @@ ]) ;; -;; [vmaxnmaq_f]) +;; [vmaxnmaq_f] +;; [vminnmaq_f] ;; -(define_insn "mve_vmaxnmaq_f" +(define_insn "@mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w")] - VMAXNMAQ_F)) + MVE_VMAXNMA_VMINNMAQ)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vmaxnma.f%# %q0, %q2" + ".f%#\t%q0, %q2" [(set_attr "type" "mve_move") ]) @@ -1472,21 +1473,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vminnmaq_f]) -;; -(define_insn "mve_vminnmaq_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VMINNMAQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vminnma.f%# %q0, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vmlaldavq_u, vmlaldavq_s]) ;; @@ -3146,18 +3132,19 @@ ]) ;; -;; [vmaxnmaq_m_f]) +;; [vmaxnmaq_m_f] +;; [vminnmaq_m_f] ;; -(define_insn "mve_vmaxnmaq_m_f" +(define_insn "@mve_q_m_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VMAXNMAQ_M_F)) + MVE_VMAXNMA_VMINNMAQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vmaxnmat.f%# %q0, %q2" + "vpst\;t.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -3180,22 +3167,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vminnmaq_m_f]) -;; -(define_insn "mve_vminnmaq_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VMINNMAQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vminnmat.f%# %q0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vmlaldavaq_s, vmlaldavaq_u]) ;; -- 2.47.2