From 2eb8e5cba7408e2a4016a8f5c48e4980abdd1d08 Mon Sep 17 00:00:00 2001 From: Haochen Gui Date: Tue, 12 Sep 2023 09:58:08 +0800 Subject: [PATCH] rs6000: call vector load/store with length only on 64-bit Power10 gcc/ PR target/96762 * config/rs6000/rs6000-string.c (expand_block_move): Call vector load/store with length only on 64-bit Power10. gcc/testsuite/ PR target/96762 * gcc.target/powerpc/pr96762.c: New. (cherry picked from commit 946b8967b905257ac9f140225db744c9a6ab91be) --- gcc/config/rs6000/rs6000-string.c | 14 ++++++++++---- gcc/testsuite/gcc.target/powerpc/pr96762.c | 13 +++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr96762.c diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c index cc75ca5848e2..b7c77372c70b 100644 --- a/gcc/config/rs6000/rs6000-string.c +++ b/gcc/config/rs6000/rs6000-string.c @@ -2811,11 +2811,17 @@ expand_block_move (rtx operands[], bool might_overlap) gen_func.mov = gen_vsx_movv2di_64bit; } else if (TARGET_BLOCK_OPS_UNALIGNED_VSX - && TARGET_POWER10 && bytes < 16 + /* Only use lxvl/stxvl on 64bit POWER10. */ + && TARGET_POWER10 + && TARGET_64BIT + && bytes < 16 && orig_bytes > 16 - && !(bytes == 1 || bytes == 2 - || bytes == 4 || bytes == 8) - && (align >= 128 || !STRICT_ALIGNMENT)) + && !(bytes == 1 + || bytes == 2 + || bytes == 4 + || bytes == 8) + && (align >= 128 + || !STRICT_ALIGNMENT)) { /* Only use lxvl/stxvl if it could replace multiple ordinary loads+stores. Also don't use it unless we likely already diff --git a/gcc/testsuite/gcc.target/powerpc/pr96762.c b/gcc/testsuite/gcc.target/powerpc/pr96762.c new file mode 100644 index 000000000000..a59deb427386 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr96762.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ + +/* Verify there is no ICE on ilp32 env. */ + +extern void foo (char *); + +void +bar (void) +{ + char zj[] = "XXXXXXXXXXXXXXXX"; + foo (zj); +} -- 2.47.2