From 2fab055251174ec82b90cbc36146ee01da69f949 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 15 Oct 2025 08:13:39 +0800 Subject: [PATCH] arm64: dts: socfpga: agilex5: Add SMMU nodes Agilex5 includes an ARM SMMU v3 (System Memory Management Unit) to provide address translation and memory protection for DMA-capable devices such as PCIe, USB, and other peripherals. This commit adds the SMMU node to the Agilex5 device tree with compatible string "arm,smmu-v3", along with its register space and interrupts. The SMMU is required to: - Enable DMA address translation for devices that cannot directly access the full physical memory space. - Provide isolation and memory protection by restricting device access to specific regions of memory, improving system security. - Support virtualization use cases by enabling safe and isolated device passthrough to guest VMs. - Align with ARM platform architecture requirements for IOMMU support. By describing the SMMU in the device tree, the Linux IOMMU framework can probe and initialize it during boot. Devices in the system can then bind to the SMMU via the `iommus` property, enabling memory translation and protection features as expected. The following devices are updated to reference the SMMU: - NAND controller - DMA controller - SPI controller This change is a necessary step toward full enablement high-speed peripherals on Agilex5. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 04e99cd7e74b6..a22cf6a211e24 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -272,6 +272,7 @@ interrupts = ; clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; cdns,board-delay-ps = <4830>; + iommus = <&smmu 4>; status = "disabled"; }; @@ -298,6 +299,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; }; dmac1: dma-controller@10dc0000 { @@ -315,6 +317,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; }; rst: rstmgr@10d11000 { @@ -323,6 +326,18 @@ #reset-cells = <1>; }; + smmu: iommu@16000000 { + compatible = "arm,smmu-v3"; + reg = <0x16000000 0x30000>; + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + status = "disabled"; + }; + spi0: spi@10da4000 { compatible = "snps,dw-apb-ssi"; reg = <0x10da4000 0x1000>; @@ -423,6 +438,7 @@ phy-names = "usb2-phy"; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; + iommus = <&smmu 6>; clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; clock-names = "otg"; status = "disabled"; -- 2.47.3