From 30ef718423e8018723087cd17be0fd9c6dfa2e53 Mon Sep 17 00:00:00 2001 From: Xu Lu Date: Tue, 8 Jul 2025 14:07:20 +0800 Subject: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs When supervisor CSRs are accessed from VU-mode, a virtual instruction exception should be raised instead of an illegal instruction. Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking) Signed-off-by: Xu Lu Reviewed-by: Anup Patel Reviewed-by: Nutty Liu Message-ID: <20250708060720.7030-1-luxu.kernel@bytedance.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8631be97c58..9bebfae3f03 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, csr_priv = get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv == (PRV_S + 1) && env->virt_enabled) { + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; -- 2.47.2