From 314862edb13d52c481ecc330c9d3fec0507cd9bb Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Thu, 19 Jun 2025 10:06:36 +0300 Subject: [PATCH] ARM: dts: microchip: sama7g5: Add cache configuration for cpu node Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7g5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index e128074137e07..381cbcfcb34a1 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -38,6 +38,16 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB + next-level-cache = <&L2>; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; // L2, 256 KB + cache-unified; + }; }; }; -- 2.47.2