From 3241ec3eca5b14e72c3e12fbf7851a54870d4f11 Mon Sep 17 00:00:00 2001 From: timurgol007 Date: Fri, 21 Nov 2025 14:06:02 +0300 Subject: [PATCH] RISC-V: Fixed opcodes for some bitmanip instructions Currently some of the instructions in bitmanip extensions can not be obtained using DECLARE_INSN macros. I generated them using riscv-opcodes and added to other opcodes. Approved-By: Nelson Chu --- include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1c649628390..bce59c7e6f7 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2159,6 +2159,33 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +/* These are only used by gdb for now. */ +#define MATCH_BCLRI_RV32 0x48001013 +#define MASK_BCLRI_RV32 0xfe00707f +#define MATCH_BEXTI_RV32 0x48005013 +#define MASK_BEXTI_RV32 0xfe00707f +#define MATCH_BINVI_RV32 0x68001013 +#define MASK_BINVI_RV32 0xfe00707f +#define MATCH_BREV8 0x68705013 +#define MASK_BREV8 0xfff0707f +#define MATCH_BSETI_RV32 0x28001013 +#define MASK_BSETI_RV32 0xfe00707f +#define MATCH_ORC_B 0x28705013 +#define MASK_ORC_B 0xfff0707f +#define MATCH_REV8 0x6b805013 +#define MASK_REV8 0xfff0707f +#define MATCH_REV8_RV32 0x69805013 +#define MASK_REV8_RV32 0xfff0707f +#define MATCH_RORI_RV32 0x60005013 +#define MASK_RORI_RV32 0xfe00707f +#define MATCH_UNZIP 0x8f05013 +#define MASK_UNZIP 0xfff0707f +#define MATCH_ZEXT_H 0x800403b +#define MASK_ZEXT_H 0xfff0707f +#define MATCH_ZEXT_H_RV32 0x8004033 +#define MASK_ZEXT_H_RV32 0xfff0707f +#define MATCH_ZIP 0x8f01013 +#define MASK_ZIP 0xfff0707f /* Zvbb/Zvkb instructions. */ #define MATCH_VANDN_VV 0x4000057 #define MASK_VANDN_VV 0xfc00707f @@ -2269,6 +2296,8 @@ #define MASK_C_SEXT_H 0xfc7f #define MATCH_C_ZEXT_W 0x9c71 #define MASK_C_ZEXT_W 0xfc7f +#define MATCH_C_SEXT_W 0x2001 +#define MASK_C_SEXT_W 0xf07f #define MATCH_C_NOT 0x9c75 #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 @@ -4370,6 +4399,7 @@ DECLARE_INSN(sd, MATCH_SD, MASK_SD) DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) @@ -4570,6 +4600,19 @@ DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) +DECLARE_INSN(bclri_rv32, MATCH_BCLRI_RV32, MASK_BCLRI_RV32) +DECLARE_INSN(bexti_rv32, MATCH_BEXTI_RV32, MASK_BEXTI_RV32) +DECLARE_INSN(binvi_rv32, MATCH_BINVI_RV32, MASK_BINVI_RV32) +DECLARE_INSN(brev8, MATCH_BREV8, MASK_BREV8) +DECLARE_INSN(bseti_rv32, MATCH_BSETI_RV32, MASK_BSETI_RV32) +DECLARE_INSN(orc_b, MATCH_ORC_B, MASK_ORC_B) +DECLARE_INSN(rev8, MATCH_REV8, MASK_REV8) +DECLARE_INSN(rev8_rv32, MATCH_REV8_RV32, MASK_REV8_RV32) +DECLARE_INSN(rori_rv32, MATCH_RORI_RV32, MASK_RORI_RV32) +DECLARE_INSN(unzip, MATCH_UNZIP, MASK_UNZIP) +DECLARE_INSN(zext_h, MATCH_ZEXT_H, MASK_ZEXT_H) +DECLARE_INSN(zext_h_rv32, MATCH_ZEXT_H_RV32, MASK_ZEXT_H_RV32) +DECLARE_INSN(zip, MATCH_ZIP, MASK_ZIP) DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) @@ -4803,6 +4846,7 @@ DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV) /* Zcb instructions. */ DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) +DECLARE_INSN(c_sext_w, MATCH_C_SEXT_W, MASK_C_SEXT_W) DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) -- 2.47.3