From 34ae3a992a0cc3240d07d69ff12a664cbb5c8be0 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 8 Oct 2024 07:28:32 -0600 Subject: [PATCH] [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT > We have cheap logical ops, so let's just move this back to the default > to take advantage of the standard branch/op hueristics. > > gcc/ChangeLog: > > PR target/116615 > * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove. > --- > There's a bunch more discussion in the bug, but it's starting to smell > like this was just a holdover from MIPS (where maybe it also shouldn't > be set). I haven't tested this, but I figured I'd send the patch to get > a little more visibility. > > I guess we should also kick off something like a SPEC run to make sure > there's no regressions? So as I noted earlier, this appears to be a nice win on the BPI. Testsuite fallout is minimal -- just the one SFB related test tripping at -Os that was also hit by Andrew P's work. After looking at it more closely, the SFB codegen and the codegen after Andrew's work should be equivalent assuming two independent ops can dispatch together. The test actually generates sensible code at -Os. It's the -Os in combination with the -fno-ssa-phiopt that causes problems. I think the best thing to do here is just skip at -Os. That still keeps a degree of testing the SFB path. Tested successfully in my tester. But will wait for the pre-commit tester to render a verdict before moving forward. PR target/116615 gcc/ * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove. gcc/testsuite/ * gcc.target/riscv/cset-sext-sfb.c: Skip for -Os. Co-authored-by: Jeff Law --- gcc/config/riscv/riscv.h | 2 -- gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 3aecb43f831..53b7b2a40ed 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -939,8 +939,6 @@ extern enum riscv_cc get_riscv_cc (const rtx use); #define TARGET_VECTOR_MISALIGN_SUPPORTED \ riscv_vector_unaligned_access_p -#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 - /* Control the assembler format that we output. */ /* Output to assembler file text saying following lines diff --git a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c index 6e9f8cc61de..1ee45b33e15 100644 --- a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c +++ b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" } } */ /* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv32 } } } */ /* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv64 } } } */ -- 2.47.2