From 38128b5761da2a0627d67ff531dbdd6b80cc680e Mon Sep 17 00:00:00 2001 From: renlin Date: Thu, 12 Nov 2015 10:14:35 +0000 Subject: [PATCH] [PATCH][ARM]Fix addsi3_compare_op2 pattern. gcc/ 2015-11-12 Renlin Li * config/arm/arm.md (addsi3_compare_op2): Make the order of assembly pattern consistent with constraint order. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230222 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/arm.md | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0b68dfaecbc0..db14b226ce81 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-11-12 Renlin Li + + * config/arm/arm.md (addsi3_compare_op2): Make the order of + assembly pattern consistent with constraint order. + 2015-11-12 Tom de Vries * gen-pass-instances.awk (handle_line): Simplify match regexp. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8ebb1bfd221e..73c308825c40 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -747,8 +747,8 @@ "TARGET_32BIT" "@ adds%?\\t%0, %1, %2 - adds%?\\t%0, %1, %2 - subs%?\\t%0, %1, #%n2" + subs%?\\t%0, %1, #%n2 + adds%?\\t%0, %1, %2" [(set_attr "conds" "set") (set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) -- 2.47.2