From 3a68ef2cccb8a7f15ca188dbffd754d112d75898 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Thu, 17 Aug 2023 14:09:18 +0800 Subject: [PATCH] RISC-V: Support RVV VFREDOSUM.VS rounding mode intrinsic API This patch would like to support the rounding mode API for the VFREDOSUM.VS as the below samples. * __riscv_vfredosum_vs_f32m1_f32m1_rm * __riscv_vfredosum_vs_f32m1_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfredosum_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfredosum_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-redosum.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 2 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 1 + .../riscv/rvv/base/float-point-redosum.c | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 65f1d9c8ff7d..ef2991359dad 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2539,6 +2539,7 @@ static CONSTEXPR const widen_reducop vwredsumu_obj; static CONSTEXPR const freducop vfredusum_obj; static CONSTEXPR const freducop vfredusum_frm_obj; static CONSTEXPR const freducop vfredosum_obj; +static CONSTEXPR const freducop vfredosum_frm_obj; static CONSTEXPR const reducop vfredmax_obj; static CONSTEXPR const reducop vfredmin_obj; static CONSTEXPR const widen_freducop vfwredusum_obj; @@ -2797,6 +2798,7 @@ BASE (vwredsumu) BASE (vfredusum) BASE (vfredusum_frm) BASE (vfredosum) +BASE (vfredosum_frm) BASE (vfredmax) BASE (vfredmin) BASE (vfwredosum) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index fd1a84f3e68d..da8412b66df9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -241,6 +241,7 @@ extern const function_base *const vwredsumu; extern const function_base *const vfredusum; extern const function_base *const vfredusum_frm; extern const function_base *const vfredosum; +extern const function_base *const vfredosum_frm; extern const function_base *const vfredmax; extern const function_base *const vfredmin; extern const function_base *const vfwredosum; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 90a83c02d52f..80e65bfb14bd 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -501,6 +501,7 @@ DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, f_vs_ops) DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops) DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) +DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) // 14.4. Vector Widening Floating-Point Reduction Instructions DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c new file mode 100644 index 000000000000..2e6a3c28a89f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfredosum_vs_f32m1_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfredosum_vs_f32m1_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_riscv_vfredosum_vs_f32m1_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfredosum_vs_f32m1_f32m1_m (vbool32_t mask, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -- 2.47.2