From 3ac022bf389d60e696e4d3156b72f3ccd6e6368b Mon Sep 17 00:00:00 2001 From: Chunyan Zhang Date: Mon, 17 Nov 2025 21:19:25 -0700 Subject: [PATCH] raid6: test: Add support for RISC-V Add RISC-V code to be compiled to allow the userspace raid6test program to be built and run on RISC-V. Signed-off-by: Chunyan Zhang Reviewed-by: Alexandre Ghiti Tested-by: Alexandre Ghiti Link: https://patch.msgid.link/20250718072711.3865118-6-zhangchunyan@iscas.ac.cn Signed-off-by: Paul Walmsley --- lib/raid6/test/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index 8f2dd2210ba83..09bbe2b14cceb 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -35,6 +35,11 @@ ifeq ($(ARCH),aarch64) HAS_NEON = yes endif +ifeq ($(findstring riscv,$(ARCH)),riscv) + CFLAGS += -I../../../arch/riscv/include -DCONFIG_RISCV=1 + HAS_RVV = yes +endif + ifeq ($(findstring ppc,$(ARCH)),ppc) CFLAGS += -I../../../arch/powerpc/include HAS_ALTIVEC := $(shell printf '$(pound)include \nvector int a;\n' |\ @@ -63,6 +68,9 @@ else ifeq ($(HAS_ALTIVEC),yes) vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o else ifeq ($(ARCH),loongarch64) OBJS += loongarch_simd.o recov_loongarch_simd.o +else ifeq ($(HAS_RVV),yes) + OBJS += rvv.o recov_rvv.o + CFLAGS += -DCONFIG_RISCV_ISA_V=1 endif .c.o: -- 2.47.3