From 3ac3093756cd00f50e63e8dcde4d278606722105 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Wed, 4 Dec 2024 10:08:12 +0800 Subject: [PATCH] RISC-V: Refactor the testcases for bswap16-0 This patch would like to refactor the testcases of bswap16-0 after sorts of optimization option passing to testcase. To fits the big lmul like m8 for asm dump check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Update the vector register RE to cover v10 - v31. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c index 605b3565b6bd..4b55c001a31d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c @@ -10,7 +10,7 @@ ** ... ** vsrl\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ ** vsll\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ -** vor\.vv\s+v[0-9]+,\s*v[0-9],\s*v[0-9]+ +** vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ TEST_UNARY_CALL (uint16_t, __builtin_bswap16) -- 2.47.2