From 3b68d751af51138567ea4825536722874f608c1e Mon Sep 17 00:00:00 2001
From: Petar Jovanovic <mips32r2@gmail.com>
Date: Thu, 26 Nov 2015 18:17:33 +0000
Subject: [PATCH] mips: add definitions of expected ISA levels

Add values of supported isa level for MIPS CPU models. This extended
information will be packed in 31:24 bits in hwcaps.


git-svn-id: svn://svn.valgrind.org/vex/trunk@3205
---
 VEX/priv/guest_mips_toIR.c |  2 +-
 VEX/priv/host_mips_isel.c  |  2 +-
 VEX/priv/main_main.c       |  7 ++++++-
 VEX/pub/libvex.h           | 21 +++++++++++++++++++--
 4 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index b72d314c97..e16e2754e2 100644
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -17290,7 +17290,7 @@ DisResult disInstr_MIPS( IRSB*        irsb_IN,
 
    mode64 = guest_arch != VexArchMIPS32;
 #if (__mips_fpr==64)
-   fp_mode64 = ((VEX_MIPS_REV(archinfo->hwcaps) == VEX_PRID_CPU_32FPR)
+   fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(archinfo->hwcaps)
                 || guest_arch == VexArchMIPS64);
 #endif
 
diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 0cde325560..1cccaa87a4 100644
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -4184,7 +4184,7 @@ HInstrArray *iselSB_MIPS ( const IRSB* bb,
 
    mode64 = arch_host != VexArchMIPS32;
 #if (__mips_fpr==64)
-   fp_mode64 = ((VEX_MIPS_REV(hwcaps_host) == VEX_PRID_CPU_32FPR)
+   fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(hwcaps_host)
                 || arch_host == VexArchMIPS64);
 #endif
 
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index 119d70120f..88f21a2946 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1738,7 +1738,12 @@ static const HChar* show_hwcaps_mips64 ( UInt hwcaps )
       return "Loongson-baseline";
    }
 
-   return "mips64-baseline";
+   /* MIPS64 baseline. */
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) {
+      return "mips64-baseline";
+   }
+
+   return "Unsupported baseline";
 }
 
 static const HChar* show_hwcaps_tilegx ( UInt hwcaps )
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 0388acc72e..b2bd476bdc 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -222,15 +222,32 @@ typedef
 #define VEX_PRID_IMP_34K                0x9500
 #define VEX_PRID_IMP_74K                0x9700
 
+/*
+ * Instead of Company Options values, bits 31:24 will be packed with
+ * additional information, such as isa level and presence of FPU unit
+ * with 32 64-bit registers.
+ */
+#define VEX_MIPS_CPU_ISA_M32R1      0x01000000
+#define VEX_MIPS_CPU_ISA_M32R2      0x02000000
+#define VEX_MIPS_CPU_ISA_M64R1      0x04000000
+#define VEX_MIPS_CPU_ISA_M64R2      0x08000000
+#define VEX_MIPS_CPU_ISA_M32R6      0x10000000
+#define VEX_MIPS_CPU_ISA_M64R6      0x20000000
 /* CPU has FPU and 32 dbl. prec. FP registers */
-#define VEX_PRID_CPU_32FPR      0x00000040
-
+#define VEX_MIPS_CPU_32FPR          0x40000000
+/* Get MIPS Extended Information */
+#define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000)
 /* Get MIPS Company ID from HWCAPS */
 #define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000)
 /* Get MIPS Processor ID from HWCAPS */
 #define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00)
 /* Get MIPS Revision from HWCAPS */
 #define VEX_MIPS_REV(x) ((x) & 0x000000FF)
+/* Check if the processor has 32 64-bit FP registers */
+#define VEX_MIPS_HAS_32_64BIT_FPRS(x) (VEX_MIPS_EX_INFO(x) | VEX_MIPS_CPU_32FPR)
+/* Check if the processor supports MIPS32R2. */
+#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) | \
+                                      VEX_MIPS_CPU_ISA_M32R2)
 /* Check if the processor supports DSP ASE Rev 2. */
 #define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
                                (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K))
-- 
2.47.2