From 3fab3d160c59d3564090997ec19bc2263ee5f76d Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Fri, 10 Feb 2017 14:18:23 +1000 Subject: [PATCH] POWER9 add scv/rfscv instruction support opcodes/ * ppc-opc.c (powerpc_opcodes) : New mnemonics. gas/ * testsuite/gas/ppc/power9.d : New tests. --- gas/ChangeLog | 4 ++++ gas/testsuite/gas/ppc/power9.d | 3 +++ gas/testsuite/gas/ppc/power9.s | 3 +++ opcodes/ChangeLog | 4 ++++ opcodes/ppc-opc.c | 4 +++- 5 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 2730c867df3..4edacf25d13 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2017-02-10 Nicholas Piggin + + * testsuite/gas/ppc/power9.d : New tests. + 2017-01-30 Maciej W. Rozycki * config/tc-mips.c (mips_ignore_branch_isa): New variable. diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d index 6f2f53a7253..9ba53d0679d 100644 --- a/gas/testsuite/gas/ppc/power9.d +++ b/gas/testsuite/gas/ppc/power9.d @@ -391,4 +391,7 @@ Disassembly of section \.text: .*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0 .*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3 .*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31 +.*: (01 00 00 44|44 00 00 01) scv 0 +.*: (e1 0f 00 44|44 00 0f e1) scv 127 +.*: (a4 00 00 4c|4c 00 00 a4) rfscv #pass diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s index 469435d9346..27f1122018a 100644 --- a/gas/testsuite/gas/ppc/power9.s +++ b/gas/testsuite/gas/ppc/power9.s @@ -382,3 +382,6 @@ power9: mffscrni 30,0 mffscrni 30,3 mffsl 31 + scv 0 + scv 127 + rfscv diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c68782e0611..21e19bc7cee 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2017-02-10 Nicholas Piggin + + * ppc-opc.c (powerpc_opcodes) : New mnemonics. + 2017-01-12 Igor Tsimbalist * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 0a71dc8a5a5..9ac779c96ae 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] = #define L2OPT L32OPT + 1 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - /* The LEV field in a POWER SVC form instruction. */ + /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ #define SVC_LEV L2OPT + 1 { 0x7f, 5, NULL, NULL, 0 }, @@ -4142,6 +4142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, +{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, @@ -4391,6 +4392,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, +{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, -- 2.47.2