From 41dfa95679fb978cac52d8719740e4e4be9707aa Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Mon, 11 Oct 2010 18:03:13 +0000 Subject: [PATCH] Fix bogus register constraints for ARM mode LDREX and STREX. Derived from a patch by Rodrigo Belem Partially fixes #253636. git-svn-id: svn://svn.valgrind.org/vex/trunk@2063 --- VEX/priv/guest_arm_toIR.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 64a059d686..4e1d740d51 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -13287,7 +13287,7 @@ DisResult disInstr_ARM_WRK ( if (0x01900F9F == (insn & 0x0FF00FFF)) { UInt rT = INSN(15,12); UInt rN = INSN(19,16); - if (rT == 15 || rN == 15 || rT == 14 /* || (rT & 1)*/) { + if (rT == 15 || rN == 15) { /* undecodable; fall through */ } else { IRTemp res; @@ -13313,8 +13313,7 @@ DisResult disInstr_ARM_WRK ( UInt rN = INSN(19,16); UInt rD = INSN(15,12); if (rT == 15 || rN == 15 || rD == 15 - || rT == 14 /* || (rT & 1)*/ - || rD == rT || rN == rT) { + || rD == rT || rD == rN) { /* undecodable; fall through */ } else { IRTemp resSC1, resSC32; -- 2.47.2