From 424b324165ea0343598c5a8b52591ea504dcde52 Mon Sep 17 00:00:00 2001 From: Mateus Lima Alves Date: Mon, 26 Jan 2026 13:05:19 -0300 Subject: [PATCH] armv7: Add CPLD support via IFC to the ls1021a-iot board. This patch adds CPLD support via IFC to the ls1021a-iot board. Signed-off-by: Mateus Lima Alves --- board/freescale/ls1021aiot/ls1021aiot.c | 5 ++++ configs/ls1021aiot_sdcard_defconfig | 1 + drivers/misc/Kconfig | 7 ++++- include/configs/ls1021aiot.h | 34 +++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 4eff0a3fee0..52a3c3abdb4 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,10 @@ int board_early_init_f(void) #endif +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + arch_soc_init(); return 0; diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 6b32150e408..78b81c1895e 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -106,3 +106,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_FSL_IFC=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dde773ab6b1..be7fdab56d1 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -694,7 +694,12 @@ config ESM_PMIC typically to reboot the board in error condition. config FSL_IFC - bool + bool "Freescale Integrated Flash Controller" + depends on ARM + help + This driver is for the Integrated Flash Controller(IFC) module + available in Freescale SoCs. This controller allows to handle + devices such as NOR, NAND, FPGA and ASIC etc. config SL28CPLD bool "Enable Kontron sl28cpld multi-function driver" diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 971a393817a..59acf00b8e5 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -44,6 +44,40 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +/* CPLD */ + +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE + +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_FPGA_FTIM3 + /* * Serial Port */ -- 2.47.3