From 43f737fb7936d78d84df36cf75ad19dbe94b0366 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 10 Dec 2023 23:13:36 -0500 Subject: [PATCH] Fixes for 6.1 Signed-off-by: Sasha Levin --- ...ix-warnings-in-amdgpu-amdgpu_display.patch | 180 ++++++++++++++++++ ...eprom-i2c-address-support-for-ip-dis.patch | 75 ++++++++ ...dd-i2c-eeprom-support-on-smu-v13_0_6.patch | 45 +++++ ...add-support-for-ras-table-at-0x40000.patch | 53 ++++++ ...ct-the-amdgpu-runtime-dereference-us.patch | 45 +++++ ...uple-ras-eeprom-addresses-from-chips.patch | 104 ++++++++++ ...u-fix-memory-overflow-in-the-ib-test.patch | 76 ++++++++ ...-remove-redundant-i2c-eeprom-address.patch | 102 ++++++++++ ...e-second-moot-switch-to-set-eeprom-i.patch | 51 +++++ ...n-from-switch-early-for-eeprom-i2c-a.patch | 70 +++++++ ...-amdgpu-simplify-amdgpu_ras_eeprom.c.patch | 132 +++++++++++++ ...e-eeprom-i2c-address-for-smu-v13_0_0.patch | 40 ++++ ...e-ras-eeprom-support-for-smu-v13_0_0.patch | 44 +++++ ...-fix-error-handling-on-failed-export.patch | 61 ++++++ .../perf-fix-perf_event_validate_size.patch | 135 +++++++++++++ queue-6.1/series | 16 ++ ...el-crash-due-to-late-update-to-read-.patch | 94 +++++++++ 17 files changed, 1323 insertions(+) create mode 100644 queue-6.1/drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch create mode 100644 queue-6.1/drm-amdgpu-add-eeprom-i2c-address-support-for-ip-dis.patch create mode 100644 queue-6.1/drm-amdgpu-add-i2c-eeprom-support-on-smu-v13_0_6.patch create mode 100644 queue-6.1/drm-amdgpu-add-support-for-ras-table-at-0x40000.patch create mode 100644 queue-6.1/drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch create mode 100644 queue-6.1/drm-amdgpu-decouple-ras-eeprom-addresses-from-chips.patch create mode 100644 queue-6.1/drm-amdgpu-fix-memory-overflow-in-the-ib-test.patch create mode 100644 queue-6.1/drm-amdgpu-remove-redundant-i2c-eeprom-address.patch create mode 100644 queue-6.1/drm-amdgpu-remove-second-moot-switch-to-set-eeprom-i.patch create mode 100644 queue-6.1/drm-amdgpu-return-from-switch-early-for-eeprom-i2c-a.patch create mode 100644 queue-6.1/drm-amdgpu-simplify-amdgpu_ras_eeprom.c.patch create mode 100644 queue-6.1/drm-amdgpu-update-eeprom-i2c-address-for-smu-v13_0_0.patch create mode 100644 queue-6.1/drm-amdgpu-update-ras-eeprom-support-for-smu-v13_0_0.patch create mode 100644 queue-6.1/gpiolib-sysfs-fix-error-handling-on-failed-export.patch create mode 100644 queue-6.1/perf-fix-perf_event_validate_size.patch create mode 100644 queue-6.1/x86-sev-fix-kernel-crash-due-to-late-update-to-read-.patch diff --git a/queue-6.1/drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch b/queue-6.1/drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch new file mode 100644 index 00000000000..ce150f60a0d --- /dev/null +++ b/queue-6.1/drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch @@ -0,0 +1,180 @@ +From 5050dfe433fdd4167a391d7465876286796d71d1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 18 Jul 2023 12:28:37 +0530 +Subject: drm/amd/amdgpu: Fix warnings in amdgpu/amdgpu_display.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Srinivasan Shanmugam + +[ Upstream commit 93125cb704919f572c01e02ef64923caff1c3164 ] + +Fixes the below checkpatch.pl warnings: + +WARNING: Block comments use * on subsequent lines +WARNING: Block comments use a trailing */ on a separate line +WARNING: suspect code indent for conditional statements (8, 12) +WARNING: braces {} are not necessary for single statement blocks + +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Srinivasan Shanmugam +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: c6df7f313794 ("drm/amdgpu: correct the amdgpu runtime dereference usage count") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 42 ++++++++++++--------- + 1 file changed, 25 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +index 2fced451f0aea..ee528ed639568 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +@@ -90,7 +90,7 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work) + + struct drm_crtc *crtc = &amdgpu_crtc->base; + unsigned long flags; +- unsigned i; ++ unsigned int i; + int vpos, hpos; + + for (i = 0; i < work->shared_count; ++i) +@@ -167,7 +167,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, + u64 tiling_flags; + int i, r; + +- work = kzalloc(sizeof *work, GFP_KERNEL); ++ work = kzalloc(sizeof(*work), GFP_KERNEL); + if (work == NULL) + return -ENOMEM; + +@@ -298,13 +298,15 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, + + adev = drm_to_adev(dev); + /* if we have active crtcs and we don't have a power ref, +- take the current one */ ++ * take the current one ++ */ + if (active && !adev->have_disp_power_ref) { + adev->have_disp_power_ref = true; + return ret; + } + /* if we have no active crtcs, then drop the power ref +- we got before */ ++ * we got before ++ */ + if (!active && adev->have_disp_power_ref) { + pm_runtime_put_autosuspend(dev->dev); + adev->have_disp_power_ref = false; +@@ -473,11 +475,10 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, + if (amdgpu_connector->router.ddc_valid) + amdgpu_i2c_router_select_ddc_port(amdgpu_connector); + +- if (use_aux) { ++ if (use_aux) + ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); +- } else { ++ else + ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); +- } + + if (ret != 2) + /* Couldn't find an accessible DDC on this connector */ +@@ -486,10 +487,12 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, + * EDID header starts with: + * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. + * Only the first 6 bytes must be valid as +- * drm_edid_block_valid() can fix the last 2 bytes */ ++ * drm_edid_block_valid() can fix the last 2 bytes ++ */ + if (drm_edid_header_is_valid(buf) < 6) { + /* Couldn't find an accessible EDID on this +- * connector */ ++ * connector ++ */ + return false; + } + return true; +@@ -1204,8 +1207,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, + + obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); + if (obj == NULL) { +- drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " +- "can't create framebuffer\n", mode_cmd->handles[0]); ++ drm_dbg_kms(dev, ++ "No GEM object associated to handle 0x%08X, can't create framebuffer\n", ++ mode_cmd->handles[0]); ++ + return ERR_PTR(-ENOENT); + } + +@@ -1398,6 +1403,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + } + if (amdgpu_crtc->rmx_type != RMX_OFF) { + fixed20_12 a, b; ++ + a.full = dfixed_const(src_v); + b.full = dfixed_const(dst_v); + amdgpu_crtc->vsc.full = dfixed_div(a, b); +@@ -1417,7 +1423,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + * + * \param dev Device to query. + * \param pipe Crtc to query. +- * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). ++ * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). + * For driver internal use only also supports these flags: + * + * USE_REAL_VBLANKSTART to use the real start of vblank instead +@@ -1493,8 +1499,8 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, + + /* Called from driver internal vblank counter query code? */ + if (flags & GET_DISTANCE_TO_VBLANKSTART) { +- /* Caller wants distance from real vbl_start in *hpos */ +- *hpos = *vpos - vbl_start; ++ /* Caller wants distance from real vbl_start in *hpos */ ++ *hpos = *vpos - vbl_start; + } + + /* Fudge vblank to start a few scanlines earlier to handle the +@@ -1516,7 +1522,7 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, + + /* In vblank? */ + if (in_vbl) +- ret |= DRM_SCANOUTPOS_IN_VBLANK; ++ ret |= DRM_SCANOUTPOS_IN_VBLANK; + + /* Called from driver internal vblank counter query code? */ + if (flags & GET_DISTANCE_TO_VBLANKSTART) { +@@ -1622,6 +1628,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) + + if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); ++ + r = amdgpu_bo_reserve(aobj, true); + if (r == 0) { + amdgpu_bo_unpin(aobj); +@@ -1629,9 +1636,9 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) + } + } + +- if (fb == NULL || fb->obj[0] == NULL) { ++ if (!fb || !fb->obj[0]) + continue; +- } ++ + robj = gem_to_amdgpu_bo(fb->obj[0]); + if (!amdgpu_display_robj_is_fb(adev, robj)) { + r = amdgpu_bo_reserve(robj, true); +@@ -1658,6 +1665,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) + + if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); ++ + r = amdgpu_bo_reserve(aobj, true); + if (r == 0) { + r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-add-eeprom-i2c-address-support-for-ip-dis.patch b/queue-6.1/drm-amdgpu-add-eeprom-i2c-address-support-for-ip-dis.patch new file mode 100644 index 00000000000..2d3719e6ebd --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-eeprom-i2c-address-support-for-ip-dis.patch @@ -0,0 +1,75 @@ +From 665d31339d23b7ab9a0f022f78d6783c4c429f3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 11 Oct 2022 15:08:38 +0800 +Subject: drm/amdgpu: Add EEPROM I2C address support for ip discovery + +From: Candice Li + +[ Upstream commit c9bdc6c3cf39df6db9c611d05fc512b1276b1cc8 ] + +1. Update EEPROM_I2C_MADDR_SMU_13_0_0 to EEPROM_I2C_MADDR_54H +2. Add EEPROM I2C address support for smu v13_0_0 and v13_0_10. + +Signed-off-by: Candice Li +Reviewed-by: Tao Zhou +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 20 +++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 7dc39154822c5..7268ae65c140c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -38,7 +38,7 @@ + #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0 + #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0 + #define EEPROM_I2C_MADDR_ALDEBARAN 0x0 +-#define EEPROM_I2C_MADDR_SMU_13_0_0 (0x54UL << 16) ++#define EEPROM_I2C_MADDR_54H (0x54UL << 16) + + /* + * The 2 macros bellow represent the actual size in bytes that +@@ -124,6 +124,19 @@ static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, + return true; + } + ++static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, ++ struct amdgpu_ras_eeprom_control *control) ++{ ++ switch (adev->ip_versions[MP1_HWIP][0]) { ++ case IP_VERSION(13, 0, 0): ++ case IP_VERSION(13, 0, 10): ++ control->i2c_address = EEPROM_I2C_MADDR_54H; ++ return true; ++ default: ++ return false; ++ } ++} ++ + static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + struct amdgpu_ras_eeprom_control *control) + { +@@ -163,13 +176,16 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN; + break; + ++ case CHIP_IP_DISCOVERY: ++ return __get_eeprom_i2c_addr_ip_discovery(adev, control); ++ + default: + return false; + } + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): +- control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0; ++ control->i2c_address = EEPROM_I2C_MADDR_54H; + break; + + default: +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-add-i2c-eeprom-support-on-smu-v13_0_6.patch b/queue-6.1/drm-amdgpu-add-i2c-eeprom-support-on-smu-v13_0_6.patch new file mode 100644 index 00000000000..4764967ee88 --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-i2c-eeprom-support-on-smu-v13_0_6.patch @@ -0,0 +1,45 @@ +From 6df7385f851a0a15d9aeced127520dfc2b1f6afe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Aug 2023 21:23:49 +0800 +Subject: drm/amdgpu: Add I2C EEPROM support on smu v13_0_6 + +From: Candice Li + +[ Upstream commit b81fde0dfe402e864ef1ac506eba756c89f1ad32 ] + +Support I2C EEPROM on smu v13_0_6. + +v2: Move IP_VERSION(13, 0, 6) ahead of IP_VERSION(13, 0, 10). + +Signed-off-by: Candice Li +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index c2827edb9d3d9..47406456e2707 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -112,6 +112,7 @@ static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) + case IP_VERSION(11, 0, 7): /* Sienna cichlid */ + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 2): /* Aldebaran */ ++ case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 10): + return true; + default: +@@ -166,6 +167,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + control->i2c_address = EEPROM_I2C_MADDR_0; + return true; + case IP_VERSION(13, 0, 0): ++ case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 10): + control->i2c_address = EEPROM_I2C_MADDR_4; + return true; +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-add-support-for-ras-table-at-0x40000.patch b/queue-6.1/drm-amdgpu-add-support-for-ras-table-at-0x40000.patch new file mode 100644 index 00000000000..2de6469b9af --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-support-for-ras-table-at-0x40000.patch @@ -0,0 +1,53 @@ +From f9856f098f312543b28ae2fadf6101d9713a9a4b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 15 Nov 2022 00:36:03 -0500 +Subject: drm/amdgpu: Add support for RAS table at 0x40000 + +From: Luben Tuikov + +[ Upstream commit 64a3dbb06ad88d89a0958ccafc4f01611657f641 ] + +Add support for RAS table at I2C EEPROM address of 0x40000, since on some +ASICs it is not at 0, but at 0x40000. + +Cc: Alex Deucher +Cc: Kent Russell +Signed-off-by: Luben Tuikov +Tested-by: Kent Russell +Reviewed-by: Kent Russell +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index f63bd31e199c8..2d9f3f4cd79e9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -157,6 +157,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, + static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + struct amdgpu_ras_eeprom_control *control) + { ++ struct atom_context *atom_ctx = adev->mode_info.atom_context; + u8 i2c_addr; + + if (!control) +@@ -190,7 +191,11 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + break; + + case CHIP_ALDEBARAN: +- control->i2c_address = EEPROM_I2C_MADDR_0; ++ if (strnstr(atom_ctx->vbios_version, "D673", ++ sizeof(atom_ctx->vbios_version))) ++ control->i2c_address = EEPROM_I2C_MADDR_4; ++ else ++ control->i2c_address = EEPROM_I2C_MADDR_0; + break; + + case CHIP_IP_DISCOVERY: +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch b/queue-6.1/drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch new file mode 100644 index 00000000000..a5ba8033ded --- /dev/null +++ b/queue-6.1/drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch @@ -0,0 +1,45 @@ +From c42b38af7e343c25f1c32dffd9d027b2298a5ab2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Nov 2023 14:38:29 +0800 +Subject: drm/amdgpu: correct the amdgpu runtime dereference usage count + +From: Prike Liang + +[ Upstream commit c6df7f313794c3ad41a49b9a7c95da369db607f3 ] + +Fix the amdgpu runpm dereference usage count. + +Signed-off-by: Prike Liang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +index ee528ed639568..aabde6ebb190e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +@@ -304,14 +304,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, + adev->have_disp_power_ref = true; + return ret; + } +- /* if we have no active crtcs, then drop the power ref +- * we got before ++ /* if we have no active crtcs, then go to ++ * drop the power ref we got before + */ +- if (!active && adev->have_disp_power_ref) { +- pm_runtime_put_autosuspend(dev->dev); ++ if (!active && adev->have_disp_power_ref) + adev->have_disp_power_ref = false; +- } +- + out: + /* drop the power reference we got coming in here */ + pm_runtime_put_autosuspend(dev->dev); +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-decouple-ras-eeprom-addresses-from-chips.patch b/queue-6.1/drm-amdgpu-decouple-ras-eeprom-addresses-from-chips.patch new file mode 100644 index 00000000000..95b9fa227b9 --- /dev/null +++ b/queue-6.1/drm-amdgpu-decouple-ras-eeprom-addresses-from-chips.patch @@ -0,0 +1,104 @@ +From 11ef104c5f80a7ad74c78acd517276d15d1b5bb5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 7 Nov 2022 12:38:03 -0500 +Subject: drm/amdgpu: Decouple RAS EEPROM addresses from chips + +From: Luben Tuikov + +[ Upstream commit 3b8164f8084ff7888ed24970efa230ff5d36eda8 ] + +Abstract RAS I2C EEPROM addresses from chip names, and set their macro +definition names to the address they set, not the chip they attach +to. Since most chips either use I2C EEPROM address 0 or 40000h for the RAS +table start offset, this leaves us with only two macro definitions as +opposed to five, and removes the redundancy of four. + +Cc: Candice Li +Cc: Tao Zhou +Cc: Alex Deucher +Signed-off-by: Luben Tuikov +Reviewed-by: Kent Russell +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 23 +++++++++---------- + 1 file changed, 11 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 1bb92a64f24af..f63bd31e199c8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -51,12 +51,11 @@ + * Depending on the size of the I2C EEPROM device(s), bits 18:16 may + * address memory in a device or a device on the I2C bus, depending on + * the status of pins 1-3. See top of amdgpu_eeprom.c. ++ * ++ * The RAS table lives either at address 0 or address 40000h of EEPROM. + */ +-#define EEPROM_I2C_MADDR_VEGA20 0x0 +-#define EEPROM_I2C_MADDR_ARCTURUS 0x40000 +-#define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0 +-#define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0 +-#define EEPROM_I2C_MADDR_ALDEBARAN 0x0 ++#define EEPROM_I2C_MADDR_0 0x0 ++#define EEPROM_I2C_MADDR_4 0x40000 + + /* + * The 2 macros bellow represent the actual size in bytes that +@@ -135,9 +134,9 @@ static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, + if (strnstr(atom_ctx->vbios_version, + "D342", + sizeof(atom_ctx->vbios_version))) +- control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342; ++ control->i2c_address = EEPROM_I2C_MADDR_0; + else +- control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS; ++ control->i2c_address = EEPROM_I2C_MADDR_4; + + return true; + } +@@ -148,7 +147,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 10): +- control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS; ++ control->i2c_address = EEPROM_I2C_MADDR_4; + return true; + default: + return false; +@@ -180,18 +179,18 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + + switch (adev->asic_type) { + case CHIP_VEGA20: +- control->i2c_address = EEPROM_I2C_MADDR_VEGA20; ++ control->i2c_address = EEPROM_I2C_MADDR_0; + break; + + case CHIP_ARCTURUS: + return __get_eeprom_i2c_addr_arct(adev, control); + + case CHIP_SIENNA_CICHLID: +- control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID; ++ control->i2c_address = EEPROM_I2C_MADDR_0; + break; + + case CHIP_ALDEBARAN: +- control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN; ++ control->i2c_address = EEPROM_I2C_MADDR_0; + break; + + case CHIP_IP_DISCOVERY: +@@ -203,7 +202,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): +- control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS; ++ control->i2c_address = EEPROM_I2C_MADDR_4; + break; + + default: +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-fix-memory-overflow-in-the-ib-test.patch b/queue-6.1/drm-amdgpu-fix-memory-overflow-in-the-ib-test.patch new file mode 100644 index 00000000000..eb86ff68129 --- /dev/null +++ b/queue-6.1/drm-amdgpu-fix-memory-overflow-in-the-ib-test.patch @@ -0,0 +1,76 @@ +From 358213288559f5bd0d1341daf9a508f194a80a94 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Nov 2023 11:06:51 +0800 +Subject: drm/amdgpu: fix memory overflow in the IB test +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Tim Huang + +[ Upstream commit 6b0b7789a7a5f3e69185449f891beea58e563f9b ] + +Fix a memory overflow issue in the gfx IB test +for some ASICs. At least 20 bytes are needed for +the IB test packet. + +v2: correct code indentation errors. (Christian) + +Signed-off-by: Tim Huang +Reviewed-by: Yifan Zhang +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- + 3 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +index 23e7e5126eae6..66a6f7a37ebcf 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -397,7 +397,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) + adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); + cpu_ptr = &adev->wb.wb[index]; + +- r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); ++ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + goto err1; +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 7f0b18b0d4c48..71ef25425c7f6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -883,8 +883,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) + gpu_addr = adev->wb.gpu_addr + (index * 4); + adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); + memset(&ib, 0, sizeof(ib)); +- r = amdgpu_ib_get(adev, NULL, 16, +- AMDGPU_IB_POOL_DIRECT, &ib); ++ ++ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); + if (r) + goto err1; + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index fe371022e5104..84ca601f7d5f3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1034,8 +1034,8 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) + gpu_addr = adev->wb.gpu_addr + (index * 4); + adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); + memset(&ib, 0, sizeof(ib)); +- r = amdgpu_ib_get(adev, NULL, 16, +- AMDGPU_IB_POOL_DIRECT, &ib); ++ ++ r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); + if (r) + goto err1; + +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-remove-redundant-i2c-eeprom-address.patch b/queue-6.1/drm-amdgpu-remove-redundant-i2c-eeprom-address.patch new file mode 100644 index 00000000000..0f9a81de745 --- /dev/null +++ b/queue-6.1/drm-amdgpu-remove-redundant-i2c-eeprom-address.patch @@ -0,0 +1,102 @@ +From 8b05e1a5a4ec2137e9ef436a548f3bf6ecbb7400 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 7 Nov 2022 12:06:44 -0500 +Subject: drm/amdgpu: Remove redundant I2C EEPROM address + +From: Luben Tuikov + +[ Upstream commit da858deab88eb561f2196bc99b6dbd2320e56456 ] + +Remove redundant EEPROM_I2C_MADDR_54H address, since we already have it +represented (ARCTURUS), and since we don't include the I2C device type +identifier in EEPROM memory addresses, i.e. that high up in the device +abstraction--we only use EEPROM memory addresses, as memory is continuously +represented by EEPROM device(s) on the I2C bus. + +Add a comment describing what these memory addresses are, how they come +about and how they're usually extracted from the device address byte. + +Cc: Candice Li +Cc: Tao Zhou +Cc: Alex Deucher +Fixes: c9bdc6c3cf39df ("drm/amdgpu: Add EEPROM I2C address support for ip discovery") +Signed-off-by: Luben Tuikov +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 2 ++ + .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 24 ++++++++++++++++--- + 2 files changed, 23 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c +index 4d9eb0137f8c4..d6c4293829aab 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c +@@ -79,6 +79,8 @@ + * That is, for an I2C EEPROM driver everything is controlled by + * the "eeprom_addr". + * ++ * See also top of amdgpu_ras_eeprom.c. ++ * + * P.S. If you need to write, lock and read the Identification Page, + * (M24M02-DR device only, which we do not use), change the "7" to + * "0xF" in the macro below, and let the client set bit 20 to 1 in +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 7268ae65c140c..1bb92a64f24af 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -33,12 +33,30 @@ + + #include "amdgpu_reset.h" + ++/* These are memory addresses as would be seen by one or more EEPROM ++ * chips strung on the I2C bus, usually by manipulating pins 1-3 of a ++ * set of EEPROM devices. They form a continuous memory space. ++ * ++ * The I2C device address includes the device type identifier, 1010b, ++ * which is a reserved value and indicates that this is an I2C EEPROM ++ * device. It also includes the top 3 bits of the 19 bit EEPROM memory ++ * address, namely bits 18, 17, and 16. This makes up the 7 bit ++ * address sent on the I2C bus with bit 0 being the direction bit, ++ * which is not represented here, and sent by the hardware directly. ++ * ++ * For instance, ++ * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. ++ * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. ++ * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. ++ * Depending on the size of the I2C EEPROM device(s), bits 18:16 may ++ * address memory in a device or a device on the I2C bus, depending on ++ * the status of pins 1-3. See top of amdgpu_eeprom.c. ++ */ + #define EEPROM_I2C_MADDR_VEGA20 0x0 + #define EEPROM_I2C_MADDR_ARCTURUS 0x40000 + #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0 + #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0 + #define EEPROM_I2C_MADDR_ALDEBARAN 0x0 +-#define EEPROM_I2C_MADDR_54H (0x54UL << 16) + + /* + * The 2 macros bellow represent the actual size in bytes that +@@ -130,7 +148,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 10): +- control->i2c_address = EEPROM_I2C_MADDR_54H; ++ control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS; + return true; + default: + return false; +@@ -185,7 +203,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): +- control->i2c_address = EEPROM_I2C_MADDR_54H; ++ control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS; + break; + + default: +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-remove-second-moot-switch-to-set-eeprom-i.patch b/queue-6.1/drm-amdgpu-remove-second-moot-switch-to-set-eeprom-i.patch new file mode 100644 index 00000000000..b1b92f47a8d --- /dev/null +++ b/queue-6.1/drm-amdgpu-remove-second-moot-switch-to-set-eeprom-i.patch @@ -0,0 +1,51 @@ +From 1e85711a1f96d0ac3ee083a25db070b5e87abcdf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Mar 2023 00:56:26 -0400 +Subject: drm/amdgpu: Remove second moot switch to set EEPROM I2C address + +From: Luben Tuikov + +[ Upstream commit 1bb745d7596d2b368fd9afb90473f3581495e39d ] + +Remove second switch since it already has its own function and case in the +first switch. This also avoids requalifying the EEPROM I2C address for VEGA20, +SIENNA CICHLID, and ALDEBARAN, as those have been set by the first switch and +shouldn't match SMU v13.0.x. + +Cc: Candice Li +Cc: Kent Russell +Cc: Alex Deucher +Fixes: 158225294683 ("drm/amdgpu: Add EEPROM I2C address for smu v13_0_0") +Fixes: c9bdc6c3cf39 ("drm/amdgpu: Add EEPROM I2C address support for ip discovery") +Signed-off-by: Luben Tuikov +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 2d9f3f4cd79e9..b908d575b5a98 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -205,15 +205,6 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + return false; + } + +- switch (adev->ip_versions[MP1_HWIP][0]) { +- case IP_VERSION(13, 0, 0): +- control->i2c_address = EEPROM_I2C_MADDR_4; +- break; +- +- default: +- break; +- } +- + return true; + } + +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-return-from-switch-early-for-eeprom-i2c-a.patch b/queue-6.1/drm-amdgpu-return-from-switch-early-for-eeprom-i2c-a.patch new file mode 100644 index 00000000000..cb4cf20eebb --- /dev/null +++ b/queue-6.1/drm-amdgpu-return-from-switch-early-for-eeprom-i2c-a.patch @@ -0,0 +1,70 @@ +From 0c1216fd2740a619c7712e26c6d0ed716dcb79ea Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Mar 2023 01:46:41 -0400 +Subject: drm/amdgpu: Return from switch early for EEPROM I2C address + +From: Luben Tuikov + +[ Upstream commit 8782007b5f5795f118c5167f46d8c8142abcc92f ] + +As soon as control->i2c_address is set, return; remove the "break;" from the +switch--it is unnecessary. This mimics what happens when for some cases in the +switch, we call helper functions with "return ". + +Remove final function "return true;" to indicate that the switch is final and +terminal, and that there should be no code after the switch. + +Cc: Candice Li +Cc: Kent Russell +Cc: Alex Deucher +Signed-off-by: Luben Tuikov +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index b908d575b5a98..40cd9d8c4e870 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -181,14 +181,14 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + switch (adev->asic_type) { + case CHIP_VEGA20: + control->i2c_address = EEPROM_I2C_MADDR_0; +- break; ++ return true; + + case CHIP_ARCTURUS: + return __get_eeprom_i2c_addr_arct(adev, control); + + case CHIP_SIENNA_CICHLID: + control->i2c_address = EEPROM_I2C_MADDR_0; +- break; ++ return true; + + case CHIP_ALDEBARAN: + if (strnstr(atom_ctx->vbios_version, "D673", +@@ -196,7 +196,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + control->i2c_address = EEPROM_I2C_MADDR_4; + else + control->i2c_address = EEPROM_I2C_MADDR_0; +- break; ++ return true; + + case CHIP_IP_DISCOVERY: + return __get_eeprom_i2c_addr_ip_discovery(adev, control); +@@ -204,8 +204,6 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + default: + return false; + } +- +- return true; + } + + static void +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-simplify-amdgpu_ras_eeprom.c.patch b/queue-6.1/drm-amdgpu-simplify-amdgpu_ras_eeprom.c.patch new file mode 100644 index 00000000000..82a7df309c1 --- /dev/null +++ b/queue-6.1/drm-amdgpu-simplify-amdgpu_ras_eeprom.c.patch @@ -0,0 +1,132 @@ +From 3b7299891cd3938175772dab91cffae814665cd3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Mar 2023 20:09:08 -0400 +Subject: drm/amdgpu: simplify amdgpu_ras_eeprom.c + +From: Alex Deucher + +[ Upstream commit 6246059a19d4cd32ef1af42a6ab016b779cd68c4 ] + +All chips that support RAS also support IP discovery, so +use the IP versions rather than a mix of IP versions and +asic types. Checking the validity of the atom_ctx pointer +is not required as the vbios is already fetched at this +point. + +v2: add comments to id asic types based on feedback from Luben + +Reviewed-by: Luben Tuikov +Signed-off-by: Alex Deucher +Cc: Luben Tuikov +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 72 ++++++------------- + 1 file changed, 20 insertions(+), 52 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 40cd9d8c4e870..c2827edb9d3d9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -106,48 +106,13 @@ + #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev + + static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) +-{ +- if (adev->asic_type == CHIP_IP_DISCOVERY) { +- switch (adev->ip_versions[MP1_HWIP][0]) { +- case IP_VERSION(13, 0, 0): +- case IP_VERSION(13, 0, 10): +- return true; +- default: +- return false; +- } +- } +- +- return adev->asic_type == CHIP_VEGA20 || +- adev->asic_type == CHIP_ARCTURUS || +- adev->asic_type == CHIP_SIENNA_CICHLID || +- adev->asic_type == CHIP_ALDEBARAN; +-} +- +-static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, +- struct amdgpu_ras_eeprom_control *control) +-{ +- struct atom_context *atom_ctx = adev->mode_info.atom_context; +- +- if (!control || !atom_ctx) +- return false; +- +- if (strnstr(atom_ctx->vbios_version, +- "D342", +- sizeof(atom_ctx->vbios_version))) +- control->i2c_address = EEPROM_I2C_MADDR_0; +- else +- control->i2c_address = EEPROM_I2C_MADDR_4; +- +- return true; +-} +- +-static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, +- struct amdgpu_ras_eeprom_control *control) + { + switch (adev->ip_versions[MP1_HWIP][0]) { ++ case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ ++ case IP_VERSION(11, 0, 7): /* Sienna cichlid */ + case IP_VERSION(13, 0, 0): ++ case IP_VERSION(13, 0, 2): /* Aldebaran */ + case IP_VERSION(13, 0, 10): +- control->i2c_address = EEPROM_I2C_MADDR_4; + return true; + default: + return false; +@@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + return true; + } + +- switch (adev->asic_type) { +- case CHIP_VEGA20: +- control->i2c_address = EEPROM_I2C_MADDR_0; ++ switch (adev->ip_versions[MP1_HWIP][0]) { ++ case IP_VERSION(11, 0, 2): ++ /* VEGA20 and ARCTURUS */ ++ if (adev->asic_type == CHIP_VEGA20) ++ control->i2c_address = EEPROM_I2C_MADDR_0; ++ else if (strnstr(atom_ctx->vbios_version, ++ "D342", ++ sizeof(atom_ctx->vbios_version))) ++ control->i2c_address = EEPROM_I2C_MADDR_0; ++ else ++ control->i2c_address = EEPROM_I2C_MADDR_4; + return true; +- +- case CHIP_ARCTURUS: +- return __get_eeprom_i2c_addr_arct(adev, control); +- +- case CHIP_SIENNA_CICHLID: ++ case IP_VERSION(11, 0, 7): + control->i2c_address = EEPROM_I2C_MADDR_0; + return true; +- +- case CHIP_ALDEBARAN: ++ case IP_VERSION(13, 0, 2): + if (strnstr(atom_ctx->vbios_version, "D673", + sizeof(atom_ctx->vbios_version))) + control->i2c_address = EEPROM_I2C_MADDR_4; + else + control->i2c_address = EEPROM_I2C_MADDR_0; + return true; +- +- case CHIP_IP_DISCOVERY: +- return __get_eeprom_i2c_addr_ip_discovery(adev, control); +- ++ case IP_VERSION(13, 0, 0): ++ case IP_VERSION(13, 0, 10): ++ control->i2c_address = EEPROM_I2C_MADDR_4; ++ return true; + default: + return false; + } +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-update-eeprom-i2c-address-for-smu-v13_0_0.patch b/queue-6.1/drm-amdgpu-update-eeprom-i2c-address-for-smu-v13_0_0.patch new file mode 100644 index 00000000000..2780b3f0813 --- /dev/null +++ b/queue-6.1/drm-amdgpu-update-eeprom-i2c-address-for-smu-v13_0_0.patch @@ -0,0 +1,40 @@ +From ec79dc5b8390316648a10707b543f6e4293c23c3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Nov 2023 09:33:47 +0800 +Subject: drm/amdgpu: Update EEPROM I2C address for smu v13_0_0 + +From: Candice Li + +[ Upstream commit e0409021e34af50e7b6f31635c8d21583d7c43dd ] + +Check smu v13_0_0 SKU type to select EEPROM I2C address. + +Signed-off-by: Candice Li +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 47406456e2707..f5f747cfe90a1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -167,6 +167,12 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, + control->i2c_address = EEPROM_I2C_MADDR_0; + return true; + case IP_VERSION(13, 0, 0): ++ if (strnstr(atom_ctx->vbios_pn, "D707", ++ sizeof(atom_ctx->vbios_pn))) ++ control->i2c_address = EEPROM_I2C_MADDR_0; ++ else ++ control->i2c_address = EEPROM_I2C_MADDR_4; ++ return true; + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 10): + control->i2c_address = EEPROM_I2C_MADDR_4; +-- +2.42.0 + diff --git a/queue-6.1/drm-amdgpu-update-ras-eeprom-support-for-smu-v13_0_0.patch b/queue-6.1/drm-amdgpu-update-ras-eeprom-support-for-smu-v13_0_0.patch new file mode 100644 index 00000000000..3b87b868fca --- /dev/null +++ b/queue-6.1/drm-amdgpu-update-ras-eeprom-support-for-smu-v13_0_0.patch @@ -0,0 +1,44 @@ +From 5eefaa8dec6f5eeb7b1cbdb6d4961e16cce17fa7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Oct 2022 16:26:37 +0800 +Subject: drm/amdgpu: Update ras eeprom support for smu v13_0_0 and v13_0_10 + +From: Candice Li + +[ Upstream commit bc22f8ec464af9e14263c3ed6a1c2be86618c804 ] + +Enable RAS EEPROM support for smu v13_0_0 and v13_0_10. + +Signed-off-by: Candice Li +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Stable-dep-of: e0409021e34a ("drm/amdgpu: Update EEPROM I2C address for smu v13_0_0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +index 84c241b9a2a13..7dc39154822c5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +@@ -90,6 +90,16 @@ + + static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) + { ++ if (adev->asic_type == CHIP_IP_DISCOVERY) { ++ switch (adev->ip_versions[MP1_HWIP][0]) { ++ case IP_VERSION(13, 0, 0): ++ case IP_VERSION(13, 0, 10): ++ return true; ++ default: ++ return false; ++ } ++ } ++ + return adev->asic_type == CHIP_VEGA20 || + adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_SIENNA_CICHLID || +-- +2.42.0 + diff --git a/queue-6.1/gpiolib-sysfs-fix-error-handling-on-failed-export.patch b/queue-6.1/gpiolib-sysfs-fix-error-handling-on-failed-export.patch new file mode 100644 index 00000000000..1aef6cdbe06 --- /dev/null +++ b/queue-6.1/gpiolib-sysfs-fix-error-handling-on-failed-export.patch @@ -0,0 +1,61 @@ +From 5a7b5e8e182b17371af4e01c1bd353568dab21c0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 16:23:07 +0100 +Subject: gpiolib: sysfs: Fix error handling on failed export + +From: Boerge Struempfel + +[ Upstream commit 95dd1e34ff5bbee93a28ff3947eceaf6de811b1a ] + +If gpio_set_transitory() fails, we should free the GPIO again. Most +notably, the flag FLAG_REQUESTED has previously been set in +gpiod_request_commit(), and should be reset on failure. + +To my knowledge, this does not affect any current users, since the +gpio_set_transitory() mainly returns 0 and -ENOTSUPP, which is converted +to 0. However the gpio_set_transitory() function calles the .set_config() +function of the corresponding GPIO chip and there are some GPIO drivers in +which some (unlikely) branches return other values like -EPROBE_DEFER, +and -EINVAL. In these cases, the above mentioned FLAG_REQUESTED would not +be reset, which results in the pin being blocked until the next reboot. + +Fixes: e10f72bf4b3e ("gpio: gpiolib: Generalise state persistence beyond sleep") +Signed-off-by: Boerge Struempfel +Reviewed-by: Andy Shevchenko +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib-sysfs.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c +index cd27bf173dec8..a64648682c72c 100644 +--- a/drivers/gpio/gpiolib-sysfs.c ++++ b/drivers/gpio/gpiolib-sysfs.c +@@ -463,14 +463,17 @@ static ssize_t export_store(struct class *class, + goto done; + + status = gpiod_set_transitory(desc, false); +- if (!status) { +- status = gpiod_export(desc, true); +- if (status < 0) +- gpiod_free(desc); +- else +- set_bit(FLAG_SYSFS, &desc->flags); ++ if (status) { ++ gpiod_free(desc); ++ goto done; + } + ++ status = gpiod_export(desc, true); ++ if (status < 0) ++ gpiod_free(desc); ++ else ++ set_bit(FLAG_SYSFS, &desc->flags); ++ + done: + if (status) + pr_debug("%s: status %d\n", __func__, status); +-- +2.42.0 + diff --git a/queue-6.1/perf-fix-perf_event_validate_size.patch b/queue-6.1/perf-fix-perf_event_validate_size.patch new file mode 100644 index 00000000000..9b768b2422a --- /dev/null +++ b/queue-6.1/perf-fix-perf_event_validate_size.patch @@ -0,0 +1,135 @@ +From 4d338b1cbe65b8f5675645a8a882278a08a1bb5e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 15:24:52 +0100 +Subject: perf: Fix perf_event_validate_size() + +From: Peter Zijlstra + +[ Upstream commit 382c27f4ed28f803b1f1473ac2d8db0afc795a1b ] + +Budimir noted that perf_event_validate_size() only checks the size of +the newly added event, even though the sizes of all existing events +can also change due to not all events having the same read_format. + +When we attach the new event, perf_group_attach(), we do re-compute +the size for all events. + +Fixes: a723968c0ed3 ("perf: Fix u16 overflows") +Reported-by: Budimir Markovic +Signed-off-by: Peter Zijlstra (Intel) +Signed-off-by: Sasha Levin +--- + kernel/events/core.c | 61 +++++++++++++++++++++++++++----------------- + 1 file changed, 38 insertions(+), 23 deletions(-) + +diff --git a/kernel/events/core.c b/kernel/events/core.c +index 8f2b9d8b9150e..0193243f65e5c 100644 +--- a/kernel/events/core.c ++++ b/kernel/events/core.c +@@ -1812,31 +1812,34 @@ static inline void perf_event__state_init(struct perf_event *event) + PERF_EVENT_STATE_INACTIVE; + } + +-static void __perf_event_read_size(struct perf_event *event, int nr_siblings) ++static int __perf_event_read_size(u64 read_format, int nr_siblings) + { + int entry = sizeof(u64); /* value */ + int size = 0; + int nr = 1; + +- if (event->attr.read_format & PERF_FORMAT_TOTAL_TIME_ENABLED) ++ if (read_format & PERF_FORMAT_TOTAL_TIME_ENABLED) + size += sizeof(u64); + +- if (event->attr.read_format & PERF_FORMAT_TOTAL_TIME_RUNNING) ++ if (read_format & PERF_FORMAT_TOTAL_TIME_RUNNING) + size += sizeof(u64); + +- if (event->attr.read_format & PERF_FORMAT_ID) ++ if (read_format & PERF_FORMAT_ID) + entry += sizeof(u64); + +- if (event->attr.read_format & PERF_FORMAT_LOST) ++ if (read_format & PERF_FORMAT_LOST) + entry += sizeof(u64); + +- if (event->attr.read_format & PERF_FORMAT_GROUP) { ++ if (read_format & PERF_FORMAT_GROUP) { + nr += nr_siblings; + size += sizeof(u64); + } + +- size += entry * nr; +- event->read_size = size; ++ /* ++ * Since perf_event_validate_size() limits this to 16k and inhibits ++ * adding more siblings, this will never overflow. ++ */ ++ return size + nr * entry; + } + + static void __perf_event_header_size(struct perf_event *event, u64 sample_type) +@@ -1886,8 +1889,9 @@ static void __perf_event_header_size(struct perf_event *event, u64 sample_type) + */ + static void perf_event__header_size(struct perf_event *event) + { +- __perf_event_read_size(event, +- event->group_leader->nr_siblings); ++ event->read_size = ++ __perf_event_read_size(event->attr.read_format, ++ event->group_leader->nr_siblings); + __perf_event_header_size(event, event->attr.sample_type); + } + +@@ -1918,24 +1922,35 @@ static void perf_event__id_header_size(struct perf_event *event) + event->id_header_size = size; + } + ++/* ++ * Check that adding an event to the group does not result in anybody ++ * overflowing the 64k event limit imposed by the output buffer. ++ * ++ * Specifically, check that the read_size for the event does not exceed 16k, ++ * read_size being the one term that grows with groups size. Since read_size ++ * depends on per-event read_format, also (re)check the existing events. ++ * ++ * This leaves 48k for the constant size fields and things like callchains, ++ * branch stacks and register sets. ++ */ + static bool perf_event_validate_size(struct perf_event *event) + { +- /* +- * The values computed here will be over-written when we actually +- * attach the event. +- */ +- __perf_event_read_size(event, event->group_leader->nr_siblings + 1); +- __perf_event_header_size(event, event->attr.sample_type & ~PERF_SAMPLE_READ); +- perf_event__id_header_size(event); ++ struct perf_event *sibling, *group_leader = event->group_leader; + +- /* +- * Sum the lot; should not exceed the 64k limit we have on records. +- * Conservative limit to allow for callchains and other variable fields. +- */ +- if (event->read_size + event->header_size + +- event->id_header_size + sizeof(struct perf_event_header) >= 16*1024) ++ if (__perf_event_read_size(event->attr.read_format, ++ group_leader->nr_siblings + 1) > 16*1024) + return false; + ++ if (__perf_event_read_size(group_leader->attr.read_format, ++ group_leader->nr_siblings + 1) > 16*1024) ++ return false; ++ ++ for_each_sibling_event(sibling, group_leader) { ++ if (__perf_event_read_size(sibling->attr.read_format, ++ group_leader->nr_siblings + 1) > 16*1024) ++ return false; ++ } ++ + return true; + } + +-- +2.42.0 + diff --git a/queue-6.1/series b/queue-6.1/series index af0011722c3..087a94f4c59 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -147,3 +147,19 @@ parisc-reduce-size-of-the-bug_table-on-64-bit-kernel.patch parisc-fix-asm-operand-number-out-of-range-build-err.patch arm64-dts-mediatek-add-missing-space-before.patch arm64-dts-mt8183-kukui-fix-underscores-in-node-names.patch +perf-fix-perf_event_validate_size.patch +x86-sev-fix-kernel-crash-due-to-late-update-to-read-.patch +gpiolib-sysfs-fix-error-handling-on-failed-export.patch +drm-amdgpu-fix-memory-overflow-in-the-ib-test.patch +drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch +drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch +drm-amdgpu-update-ras-eeprom-support-for-smu-v13_0_0.patch +drm-amdgpu-add-eeprom-i2c-address-support-for-ip-dis.patch +drm-amdgpu-remove-redundant-i2c-eeprom-address.patch +drm-amdgpu-decouple-ras-eeprom-addresses-from-chips.patch +drm-amdgpu-add-support-for-ras-table-at-0x40000.patch +drm-amdgpu-remove-second-moot-switch-to-set-eeprom-i.patch +drm-amdgpu-return-from-switch-early-for-eeprom-i2c-a.patch +drm-amdgpu-simplify-amdgpu_ras_eeprom.c.patch +drm-amdgpu-add-i2c-eeprom-support-on-smu-v13_0_6.patch +drm-amdgpu-update-eeprom-i2c-address-for-smu-v13_0_0.patch diff --git a/queue-6.1/x86-sev-fix-kernel-crash-due-to-late-update-to-read-.patch b/queue-6.1/x86-sev-fix-kernel-crash-due-to-late-update-to-read-.patch new file mode 100644 index 00000000000..559f6c1fd6a --- /dev/null +++ b/queue-6.1/x86-sev-fix-kernel-crash-due-to-late-update-to-read-.patch @@ -0,0 +1,94 @@ +From d7460400c05eb1c2bc23de739bd6d2f1c9001e56 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Nov 2023 16:10:29 +0530 +Subject: x86/sev: Fix kernel crash due to late update to read-only + ghcb_version + +From: Ashwin Dayanand Kamat + +[ Upstream commit 27d25348d42161837be08fc63b04a2559d2e781c ] + +A write-access violation page fault kernel crash was observed while running +cpuhotplug LTP testcases on SEV-ES enabled systems. The crash was +observed during hotplug, after the CPU was offlined and the process +was migrated to different CPU. setup_ghcb() is called again which +tries to update ghcb_version in sev_es_negotiate_protocol(). Ideally this +is a read_only variable which is initialised during booting. + +Trying to write it results in a pagefault: + + BUG: unable to handle page fault for address: ffffffffba556e70 + #PF: supervisor write access in kernel mode + #PF: error_code(0x0003) - permissions violation + [ ...] + Call Trace: + + ? __die_body.cold+0x1a/0x1f + ? __die+0x2a/0x35 + ? page_fault_oops+0x10c/0x270 + ? setup_ghcb+0x71/0x100 + ? __x86_return_thunk+0x5/0x6 + ? search_exception_tables+0x60/0x70 + ? __x86_return_thunk+0x5/0x6 + ? fixup_exception+0x27/0x320 + ? kernelmode_fixup_or_oops+0xa2/0x120 + ? __bad_area_nosemaphore+0x16a/0x1b0 + ? kernel_exc_vmm_communication+0x60/0xb0 + ? bad_area_nosemaphore+0x16/0x20 + ? do_kern_addr_fault+0x7a/0x90 + ? exc_page_fault+0xbd/0x160 + ? asm_exc_page_fault+0x27/0x30 + ? setup_ghcb+0x71/0x100 + ? setup_ghcb+0xe/0x100 + cpu_init_exception_handling+0x1b9/0x1f0 + +The fix is to call sev_es_negotiate_protocol() only in the BSP boot phase, +and it only needs to be done once in any case. + +[ mingo: Refined the changelog. ] + +Fixes: 95d33bfaa3e1 ("x86/sev: Register GHCB memory when SEV-SNP is active") +Suggested-by: Tom Lendacky +Co-developed-by: Bo Gan +Signed-off-by: Bo Gan +Signed-off-by: Ashwin Dayanand Kamat +Signed-off-by: Ingo Molnar +Acked-by: Tom Lendacky +Link: https://lore.kernel.org/r/1701254429-18250-1-git-send-email-kashwindayan@vmware.com +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/sev.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c +index 68b2a9d3dbc6b..c8dfb0fdde7f9 100644 +--- a/arch/x86/kernel/sev.c ++++ b/arch/x86/kernel/sev.c +@@ -1279,10 +1279,6 @@ void setup_ghcb(void) + if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) + return; + +- /* First make sure the hypervisor talks a supported protocol. */ +- if (!sev_es_negotiate_protocol()) +- sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); +- + /* + * Check whether the runtime #VC exception handler is active. It uses + * the per-CPU GHCB page which is set up by sev_es_init_vc_handling(). +@@ -1297,6 +1293,13 @@ void setup_ghcb(void) + return; + } + ++ /* ++ * Make sure the hypervisor talks a supported protocol. ++ * This gets called only in the BSP boot phase. ++ */ ++ if (!sev_es_negotiate_protocol()) ++ sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); ++ + /* + * Clear the boot_ghcb. The first exception comes in before the bss + * section is cleared. +-- +2.42.0 + -- 2.47.3