From 445d9f2bcb19aff832028347328334a1482c8163 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 17 Feb 2026 13:45:48 +0100 Subject: [PATCH] 6.6-stable patches added patches: cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch loongarch-add-writecombine-support-for-dmw-based-ioremap.patch --- ...g-adaptation-for-cpuset_is_populated.patch | 40 +++++ ...ombine-support-for-dmw-based-ioremap.patch | 165 ++++++++++++++++++ queue-6.6/series | 2 + 3 files changed, 207 insertions(+) create mode 100644 queue-6.6/cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch create mode 100644 queue-6.6/loongarch-add-writecombine-support-for-dmw-based-ioremap.patch diff --git a/queue-6.6/cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch b/queue-6.6/cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch new file mode 100644 index 0000000000..f59c625240 --- /dev/null +++ b/queue-6.6/cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch @@ -0,0 +1,40 @@ +From chenridong@huaweicloud.com Tue Feb 17 13:36:53 2026 +From: Chen Ridong +Date: Wed, 14 Jan 2026 01:51:29 +0000 +Subject: cpuset: Fix missing adaptation for cpuset_is_populated +To: gregkh@linuxfoundation.org +Cc: stable@vger.kernel.org, chenridong@huaweicloud.com, lujialin4@huawei.com +Message-ID: <20260114015129.1156361-1-chenridong@huaweicloud.com> + +From: Chen Ridong + +Commit b1bcaed1e39a ("cpuset: Treat cpusets in attaching as populated") +was backported to the long‑term support (LTS) branches. However, because +commit d5cf4d34a333 ("cgroup/cpuset: Don't track # of local child +partitions") was not backported, a corresponding adaptation to the +backported code is still required. + +To ensure correct behavior, replace cgroup_is_populated with +cpuset_is_populated in the partition_is_populated function. + +Cc: stable@vger.kernel.org # 6.1+ +Fixes: b1bcaed1e39a ("cpuset: Treat cpusets in attaching as populated") +Cc: Waiman Long +Cc: Tejun Heo +Signed-off-by: Chen Ridong +Signed-off-by: Greg Kroah-Hartman +--- + kernel/cgroup/cpuset.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/kernel/cgroup/cpuset.c ++++ b/kernel/cgroup/cpuset.c +@@ -486,7 +486,7 @@ static inline bool partition_is_populate + cs->attach_in_progress) + return true; + if (!excluded_child && !cs->nr_subparts_cpus) +- return cgroup_is_populated(cs->css.cgroup); ++ return cpuset_is_populated(cs); + + rcu_read_lock(); + cpuset_for_each_descendant_pre(cp, pos_css, cs) { diff --git a/queue-6.6/loongarch-add-writecombine-support-for-dmw-based-ioremap.patch b/queue-6.6/loongarch-add-writecombine-support-for-dmw-based-ioremap.patch new file mode 100644 index 0000000000..d927ad0c99 --- /dev/null +++ b/queue-6.6/loongarch-add-writecombine-support-for-dmw-based-ioremap.patch @@ -0,0 +1,165 @@ +From 8e02c3b782ec64343f3cccc8dc5a8be2b379e80b Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Sat, 20 Jul 2024 22:40:59 +0800 +Subject: LoongArch: Add writecombine support for DMW-based ioremap() + +From: Huacai Chen + +commit 8e02c3b782ec64343f3cccc8dc5a8be2b379e80b upstream. + +Currently, only TLB-based ioremap() support writecombine, so add the +counterpart for DMW-based ioremap() with help of DMW2. The base address +(WRITECOMBINE_BASE) is configured as 0xa000000000000000. + +DMW3 is unused by kernel now, however firmware may leave garbage in them +and interfere kernel's address mapping. So clear it as necessary. + +BTW, centralize the DMW configuration to macro SETUP_DMWINS. + +Signed-off-by: Jiaxun Yang +Signed-off-by: Huacai Chen +Signed-off-by: Greg Kroah-Hartman +--- + arch/loongarch/include/asm/addrspace.h | 4 ++++ + arch/loongarch/include/asm/io.h | 10 ++++++++-- + arch/loongarch/include/asm/loongarch.h | 10 +++++++++- + arch/loongarch/include/asm/stackframe.h | 11 +++++++++++ + arch/loongarch/kernel/head.S | 11 ++--------- + arch/loongarch/power/suspend_asm.S | 6 +----- + drivers/firmware/efi/libstub/loongarch.c | 2 ++ + 7 files changed, 37 insertions(+), 17 deletions(-) + +--- a/arch/loongarch/include/asm/addrspace.h ++++ b/arch/loongarch/include/asm/addrspace.h +@@ -36,6 +36,10 @@ extern unsigned long vm_map_base; + #define UNCACHE_BASE CSR_DMW0_BASE + #endif + ++#ifndef WRITECOMBINE_BASE ++#define WRITECOMBINE_BASE CSR_DMW2_BASE ++#endif ++ + #define DMW_PABITS 48 + #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1) + +--- a/arch/loongarch/include/asm/io.h ++++ b/arch/loongarch/include/asm/io.h +@@ -30,10 +30,16 @@ extern void __init early_iounmap(void __ + static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, + unsigned long prot_val) + { +- if (prot_val & _CACHE_CC) ++ switch (prot_val & _CACHE_MASK) { ++ case _CACHE_CC: + return (void __iomem *)(unsigned long)(CACHE_BASE + offset); +- else ++ case _CACHE_SUC: + return (void __iomem *)(unsigned long)(UNCACHE_BASE + offset); ++ case _CACHE_WUC: ++ return (void __iomem *)(unsigned long)(WRITECOMBINE_BASE + offset); ++ default: ++ return NULL; ++ } + } + + #define ioremap(offset, size) \ +--- a/arch/loongarch/include/asm/loongarch.h ++++ b/arch/loongarch/include/asm/loongarch.h +@@ -856,7 +856,7 @@ + #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */ + #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ + +-/* Direct Map window 0/1 */ ++/* Direct Map window 0/1/2/3 */ + #define CSR_DMW0_PLV0 _CONST64_(1 << 0) + #define CSR_DMW0_VSEG _CONST64_(0x8000) + #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) +@@ -868,6 +868,14 @@ + #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) + #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) + ++#define CSR_DMW2_PLV0 _CONST64_(1 << 0) ++#define CSR_DMW2_MAT _CONST64_(2 << 4) ++#define CSR_DMW2_VSEG _CONST64_(0xa000) ++#define CSR_DMW2_BASE (CSR_DMW2_VSEG << DMW_PABITS) ++#define CSR_DMW2_INIT (CSR_DMW2_BASE | CSR_DMW2_MAT | CSR_DMW2_PLV0) ++ ++#define CSR_DMW3_INIT 0x0 ++ + /* Performance Counter registers */ + #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ + #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */ +--- a/arch/loongarch/include/asm/stackframe.h ++++ b/arch/loongarch/include/asm/stackframe.h +@@ -37,6 +37,17 @@ + cfi_restore \reg \offset \docfi + .endm + ++ .macro SETUP_DMWINS temp ++ li.d \temp, CSR_DMW0_INIT # WUC, PLV0, 0x8000 xxxx xxxx xxxx ++ csrwr \temp, LOONGARCH_CSR_DMWIN0 ++ li.d \temp, CSR_DMW1_INIT # CAC, PLV0, 0x9000 xxxx xxxx xxxx ++ csrwr \temp, LOONGARCH_CSR_DMWIN1 ++ li.d \temp, CSR_DMW2_INIT # WUC, PLV0, 0xa000 xxxx xxxx xxxx ++ csrwr \temp, LOONGARCH_CSR_DMWIN2 ++ li.d \temp, CSR_DMW3_INIT # 0x0, unused ++ csrwr \temp, LOONGARCH_CSR_DMWIN3 ++ .endm ++ + /* Jump to the runtime virtual address. */ + .macro JUMP_VIRT_ADDR temp1 temp2 + li.d \temp1, CACHE_BASE +--- a/arch/loongarch/kernel/head.S ++++ b/arch/loongarch/kernel/head.S +@@ -44,11 +44,7 @@ SYM_DATA(kernel_fsize, .long _kernel_fsi + SYM_CODE_START(kernel_entry) # kernel entry point + + /* Config direct window and set PG */ +- li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx +- csrwr t0, LOONGARCH_CSR_DMWIN0 +- li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx +- csrwr t0, LOONGARCH_CSR_DMWIN1 +- ++ SETUP_DMWINS t0 + JUMP_VIRT_ADDR t0, t1 + + /* Enable PG */ +@@ -119,11 +115,8 @@ SYM_CODE_END(kernel_entry) + * function after setting up the stack and tp registers. + */ + SYM_CODE_START(smpboot_entry) +- li.d t0, CSR_DMW0_INIT # UC, PLV0 +- csrwr t0, LOONGARCH_CSR_DMWIN0 +- li.d t0, CSR_DMW1_INIT # CA, PLV0 +- csrwr t0, LOONGARCH_CSR_DMWIN1 + ++ SETUP_DMWINS t0 + JUMP_VIRT_ADDR t0, t1 + + /* Enable PG */ +--- a/arch/loongarch/power/suspend_asm.S ++++ b/arch/loongarch/power/suspend_asm.S +@@ -73,11 +73,7 @@ SYM_FUNC_START(loongarch_suspend_enter) + * Reload all of the registers and return. + */ + SYM_INNER_LABEL(loongarch_wakeup_start, SYM_L_GLOBAL) +- li.d t0, CSR_DMW0_INIT # UC, PLV0 +- csrwr t0, LOONGARCH_CSR_DMWIN0 +- li.d t0, CSR_DMW1_INIT # CA, PLV0 +- csrwr t0, LOONGARCH_CSR_DMWIN1 +- ++ SETUP_DMWINS t0 + JUMP_VIRT_ADDR t0, t1 + + /* Enable PG */ +--- a/drivers/firmware/efi/libstub/loongarch.c ++++ b/drivers/firmware/efi/libstub/loongarch.c +@@ -74,6 +74,8 @@ efi_status_t efi_boot_kernel(void *handl + /* Config Direct Mapping */ + csr_write64(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0); + csr_write64(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1); ++ csr_write64(CSR_DMW2_INIT, LOONGARCH_CSR_DMWIN2); ++ csr_write64(CSR_DMW3_INIT, LOONGARCH_CSR_DMWIN3); + + real_kernel_entry = (void *)kernel_entry_address(kernel_addr, image); + diff --git a/queue-6.6/series b/queue-6.6/series index 09f4f0212f..3a55e98191 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -26,3 +26,5 @@ mm-hugetlb-fix-copy_hugetlb_page_range-to-use-pt_share_count.patch mm-hugetlb-fix-hugetlb_pmd_shared.patch mm-hugetlb-fix-two-comments-related-to-huge_pmd_unshare.patch mm-hugetlb-fix-excessive-ipi-broadcasts-when-unsharing-pmd-tables-using-mmu_gather.patch +cpuset-fix-missing-adaptation-for-cpuset_is_populated.patch +loongarch-add-writecombine-support-for-dmw-based-ioremap.patch -- 2.47.3