From 4c49d5080fdae63e4d190486edbad6379a7f95d9 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 28 Oct 2009 09:21:53 +0000 Subject: [PATCH] Add support for some more Intel cache descriptors to stop Core i7 based systems moaning. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10913 --- cachegrind/cg-x86-amd64.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/cachegrind/cg-x86-amd64.c b/cachegrind/cg-x86-amd64.c index ef52753758..8293cb22b9 100644 --- a/cachegrind/cg-x86-amd64.c +++ b/cachegrind/cg-x86-amd64.c @@ -97,15 +97,17 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) /* TLB info, ignore */ case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: - case 0x4f: case 0x50: case 0x51: case 0x52: + case 0x4f: case 0x50: case 0x51: case 0x52: case 0x55: case 0x56: case 0x57: case 0x59: - case 0x5b: case 0x5c: case 0x5d: - case 0xb0: case 0xb1: + case 0x5a: case 0x5b: case 0x5c: case 0x5d: + case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xba: case 0xc0: + case 0xca: break; case 0x06: *I1c = (cache_t) { 8, 4, 32 }; break; case 0x08: *I1c = (cache_t) { 16, 4, 32 }; break; + case 0x09: *I1c = (cache_t) { 32, 4, 64 }; break; case 0x30: *I1c = (cache_t) { 32, 8, 64 }; break; case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break; @@ -121,9 +123,13 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) case 0x22: case 0x23: case 0x25: case 0x29: case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d: + case 0xe2: case 0xe3: case 0xe4: case 0xea: case 0xeb: case 0xec: VG_(dmsg)("warning: L3 cache detected but ignored\n"); break; + /* Described as "MLC" in Intel documentation */ + case 0x21: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; + /* These are sectored, whatever that means */ case 0x39: *L2c = (cache_t) { 128, 4, 64 }; L2_found = True; break; case 0x3c: *L2c = (cache_t) { 256, 4, 64 }; L2_found = True; break; -- 2.47.2