From 4e1b09d90bdfc79b2a024121a1f3b5e41c80de81 Mon Sep 17 00:00:00 2001 From: Suravee Suthikulpanit Date: Thu, 15 Jan 2026 06:08:12 +0000 Subject: [PATCH] iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() To help avoid duplicate logic when programing DTE for nested translation. Note that this commit changes behavior of when the IOMMU driver is switching domain during attach and the blocking domain, where DTE bit fields for interrupt pass-through (i.e. Lint0, Lint1, NMI, INIT, ExtInt) and System management message could be affected. These DTE bits are specified in the IVRS table for specific devices, and should be persistent. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Suravee Suthikulpanit Signed-off-by: Joerg Roedel --- drivers/iommu/amd/amd_iommu.h | 13 +++++++++++++ drivers/iommu/amd/iommu.c | 11 ----------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index aa29afe96e90e..00fc9c6073de2 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -197,9 +197,22 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, static inline void amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table_entry *new) { + struct dev_table_entry *initial_dte; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); + /* All existing DTE must have V bit set */ new->data128[0] = DTE_FLAG_V; new->data128[1] = 0; + + /* + * Restore cached persistent DTE bits, which can be set by information + * in IVRS table. See set_dev_entry_from_acpi(). + */ + initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid); + if (initial_dte) { + new->data128[0] |= initial_dte->data128[0]; + new->data128[1] |= initial_dte->data128[1]; + } } /* NESTED */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 9d2c88aa5c5f6..debc33cd4bea0 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2110,7 +2110,6 @@ static void set_dte_entry(struct amd_iommu *iommu, { u16 domid; u32 old_domid; - struct dev_table_entry *initial_dte; struct dev_table_entry new = {}; struct protection_domain *domain = dev_data->domain; struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; @@ -2168,16 +2167,6 @@ static void set_dte_entry(struct amd_iommu *iommu, old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; new.data[1] |= domid; - /* - * Restore cached persistent DTE bits, which can be set by information - * in IVRS table. See set_dev_entry_from_acpi(). - */ - initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid); - if (initial_dte) { - new.data128[0] |= initial_dte->data128[0]; - new.data128[1] |= initial_dte->data128[1]; - } - set_dte_gcr3_table(iommu, dev_data, &new); amd_iommu_update_dte(iommu, dev_data, &new); -- 2.47.3