From 4e3f3add4941a5751df05e733ccccf36d05d512c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 24 Jun 2025 20:00:41 +0300 Subject: [PATCH] drm/i915: Set PKG_C_LATENCY.added_wake_time to 0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit AFAIK PKG_C_LATENCY.added_wake_time only matters for flip queue. As long as we're not using that there's no point in adding any extra wake time. Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-2-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index f234a3aa3d15b..855bbce889c84 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -33,12 +33,6 @@ #include "skl_watermark.h" #include "skl_watermark_regs.h" -/*It is expected that DSB can do posted writes to every register in - * the pipe and planes within 100us. For flip queue use case, the - * recommended DSB execution time is 100us + one SAGV block time. - */ -#define DSB_EXE_TIME 100 - struct intel_dbuf_state { struct intel_global_state base; @@ -2899,9 +2893,6 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state) } if (fixed_refresh_rate) { - added_wake_time = DSB_EXE_TIME + - display->sagv.block_time_us; - latency = skl_watermark_max_latency(display, 1); /* Wa_22020432604 */ -- 2.47.2