From 4ee667bfdf107d9b0e19e893c13543627795dcd8 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Mon, 28 Jun 1999 19:59:20 -0600 Subject: [PATCH] mips.md (leasi, leadi): New patterns. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit � * mips.md (leasi, leadi): New patterns. From-SVN: r27826 --- gcc/config/mips/mips.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 6dde18bf3720..81c5cd38e381 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -10416,3 +10416,27 @@ move\\t%0,%z4\\n\\ [(set_attr "type" "branch") (set_attr "mode" "none") (set_attr "length" "2")]) + +;; For the rare case where we need to load an address into a register +;; that can not be recognized by the normal movsi/addsi instructions. +;; I have no idea how many insns this can actually generate. It should +;; be rare, so over-estimating as 10 instructions should not have any +;; real performance impact. +(define_insn "leasi" + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "address_operand" "p"))] + "Pmode == SImode" + "la %0,%a1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "10")]) + +;; Similarly for targets where we have 64bit pointers. +(define_insn "leadi" + [(set (match_operand:DI 0 "register_operand" "=d") + (match_operand:DI 1 "address_operand" "p"))] + "Pmode == DImode" + "la %0,%a1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "10")]) -- 2.47.2