From 4fcefdf990cb14a3586e622ded7a18c287cf51e4 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Tue, 18 Nov 2025 15:28:30 +0200 Subject: [PATCH] drm/i915/cx0: Add MTL+ .update_active_dpll hook Add .update_active_dpll function pointer to support dpll framework. Reuse ICL function pointer. v2: Add check for !HAS_LT_PHY (Suraj) v3: Remove the incorrect !HAS_LT_PHY condition and check for existing dpll_mgr Signed-off-by: Mika Kahola Reviewed-by: Suraj Kandpal # v1 Reviewed-by: Suraj Kandpal Link: https://lore.kernel.org/r/20251118132830.2584422-1-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 002ccd47856d0..39d87bc915718 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3667,8 +3667,8 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; - /* FIXME: Add MTL pll_mgr */ - if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) + /* FIXME: Add NVL+ and DG2 pll_mgr */ + if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) return; for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c45f18201ee89..e6dd6f1123d6f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = { .compute_dplls = mtl_compute_dplls, .get_dplls = mtl_get_dplls, .put_dplls = icl_put_dplls, + .update_active_dpll = icl_update_active_dpll, }; /** -- 2.47.3