From 5337627ca495cb7931a4c6fa0701a3e4c0c4ed1b Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 8 May 2025 18:09:16 +0200 Subject: [PATCH] qualcommax: use upstream QMP pipe patch Passing QMP pipe clocks was upstreamed, but it requires conversion single QMP node, so backport both of those instead of our downstream patch. Signed-off-by: Robert Marko --- ...pq8074-switch-PCIe-QMP-PHY-to-new-st.patch | 122 ++++++++++++++++++ ...q8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch} | 23 +++- ...qcom-ipq8074-use-msi-parent-for-PCIe.patch | 6 +- ...com-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch | 4 +- ...0121-arm64-dts-ipq8074-Add-WLAN-node.patch | 2 +- ...64-dts-qcom-ipq8074-add-QFPROM-fuses.patch | 2 +- 6 files changed, 145 insertions(+), 14 deletions(-) create mode 100644 target/linux/qualcommax/patches-6.6/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch rename target/linux/qualcommax/patches-6.6/{0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch => 0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch} (55%) diff --git a/target/linux/qualcommax/patches-6.6/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch b/target/linux/qualcommax/patches-6.6/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch new file mode 100644 index 00000000000..b85d073b9de --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch @@ -0,0 +1,122 @@ +From 9e5e778f3340a687dd91c533064f963d352921c6 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov +Date: Sun, 20 Aug 2023 17:20:26 +0300 +Subject: [PATCH] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style + of bindings + +Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single +resource region, no per-PHY subnodes). + +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230820142035.89903-10-dmitry.baryshkov@linaro.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 67 +++++++++++---------------- + 1 file changed, 28 insertions(+), 39 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -211,59 +211,48 @@ + + pcie_qmp0: phy@84000 { + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; +- reg = <0x00084000 0x1bc>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; ++ reg = <0x00084000 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, +- <&gcc GCC_PCIE0_AHB_CLK>; +- clock-names = "aux", "cfg_ahb"; ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "aux", ++ "cfg_ahb", ++ "pipe"; ++ ++ clock-output-names = "pcie20_phy0_pipe_clk"; ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ + resets = <&gcc GCC_PCIE0_PHY_BCR>, +- <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; +- +- pcie_phy0: phy@84200 { +- reg = <0x84200 0x16c>, +- <0x84400 0x200>, +- <0x84800 0x1f0>, +- <0x84c00 0xf4>; +- #phy-cells = <0>; +- #clock-cells = <0>; +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "pcie20_phy0_pipe_clk"; +- }; + }; + + pcie_qmp1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x0008e000 0x1c4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; ++ reg = <0x0008e000 0x1000>; + + clocks = <&gcc GCC_PCIE1_AUX_CLK>, +- <&gcc GCC_PCIE1_AHB_CLK>; +- clock-names = "aux", "cfg_ahb"; ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "aux", ++ "cfg_ahb", ++ "pipe"; ++ ++ clock-output-names = "pcie20_phy1_pipe_clk"; ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ + resets = <&gcc GCC_PCIE1_PHY_BCR>, +- <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; +- +- pcie_phy1: phy@8e200 { +- reg = <0x8e200 0x130>, +- <0x8e400 0x200>, +- <0x8e800 0x1f8>; +- #phy-cells = <0>; +- #clock-cells = <0>; +- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; +- clock-names = "pipe0"; +- clock-output-names = "pcie20_phy1_pipe_clk"; +- }; + }; + + mdio: mdio@90000 { +@@ -839,7 +828,7 @@ + #address-cells = <3>; + #size-cells = <2>; + +- phys = <&pcie_phy1>; ++ phys = <&pcie_qmp1>; + phy-names = "pciephy"; + + ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ +@@ -901,7 +890,7 @@ + #address-cells = <3>; + #size-cells = <2>; + +- phys = <&pcie_phy0>; ++ phys = <&pcie_qmp0>; + phy-names = "pciephy"; + + ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ diff --git a/target/linux/qualcommax/patches-6.6/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch b/target/linux/qualcommax/patches-6.6/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch similarity index 55% rename from target/linux/qualcommax/patches-6.6/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch rename to target/linux/qualcommax/patches-6.6/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch index 9753fa84d33..e1bdf01ded5 100644 --- a/target/linux/qualcommax/patches-6.6/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch +++ b/target/linux/qualcommax/patches-6.6/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch @@ -1,6 +1,6 @@ -From 8a576b5bc9f0555d1d970cacabcaa24a3b74fa57 Mon Sep 17 00:00:00 2001 +From 591da388c344f934601548cb44f54eab012c6c94 Mon Sep 17 00:00:00 2001 From: Robert Marko -Date: Wed, 16 Nov 2022 22:15:01 +0100 +Date: Fri, 13 Oct 2023 18:39:34 +0200 Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to GCC @@ -11,20 +11,29 @@ If not passed directly, driver maintains backwards compatibility by then falling back to global lookup. Signed-off-by: Robert Marko +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20231013164025.3541606-2-robimarko@gmail.com +Signed-off-by: Bjorn Andersson --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -407,8 +407,8 @@ +@@ -371,8 +371,14 @@ gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; - clocks = <&xo>, <&sleep_clk>; - clock-names = "xo", "sleep_clk"; -+ clocks = <&xo>, <&sleep_clk>, <&pcie_phy0>, <&pcie_phy1>; -+ clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe"; ++ clocks = <&xo>, ++ <&sleep_clk>, ++ <&pcie_qmp0>, ++ <&pcie_qmp1>; ++ clock-names = "xo", ++ "sleep_clk", ++ "pcie0_pipe", ++ "pcie1_pipe"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch b/target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch index fdf7f84b92f..24f5711373a 100644 --- a/target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch +++ b/target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch @@ -12,7 +12,7 @@ Signed-off-by: Robert Marko --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -757,7 +757,7 @@ +@@ -752,7 +752,7 @@ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; ranges = <0 0xb00a000 0xffd>; @@ -21,7 +21,7 @@ Signed-off-by: Robert Marko compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xffd>; -@@ -870,8 +870,7 @@ +@@ -865,8 +865,7 @@ ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ @@ -31,7 +31,7 @@ Signed-off-by: Robert Marko #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 142 -@@ -932,8 +931,7 @@ +@@ -927,8 +926,7 @@ ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ diff --git a/target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch b/target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch index 07f51441082..0988cb1a234 100644 --- a/target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch +++ b/target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch @@ -49,7 +49,7 @@ Signed-off-by: Robert Marko soc: soc@0 { #address-cells = <1>; #size-cells = <1>; -@@ -425,6 +451,11 @@ +@@ -420,6 +446,11 @@ reg = <0x01937000 0x21000>; }; @@ -61,7 +61,7 @@ Signed-off-by: Robert Marko spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, -@@ -972,6 +1003,56 @@ +@@ -967,6 +998,56 @@ "axi_s_sticky"; status = "disabled"; }; diff --git a/target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch index ef34c50eca5..e1b31078f34 100644 --- a/target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch +++ b/target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Robert Marko --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -1053,6 +1053,117 @@ +@@ -1048,6 +1048,117 @@ }; }; }; diff --git a/target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch b/target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch index 7730ad89f57..1e98c9a4672 100644 --- a/target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch +++ b/target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch @@ -12,7 +12,7 @@ Signed-off-by: Robert Marko --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -349,6 +349,106 @@ +@@ -338,6 +338,106 @@ reg = <0x000a4000 0x2000>; #address-cells = <1>; #size-cells = <1>; -- 2.47.2