From 58c1c98db4eb8a66ddea228ab00c8ac1bd7e027c Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Thu, 14 Jun 2018 15:34:38 +0000 Subject: [PATCH] mips64: update tests for N32 ABI Fix n32/n64 types mismatch in none, memcheck and helgrind tests. BZ issue - #345763. Contributed by: Dimitrije Nikolic, Aleksandar Rikalo, Tamara Vlahovic. --- helgrind/tests/annotate_hbefore.c | 4 +-- memcheck/tests/atomic_incs.c | 25 +++++++++--------- memcheck/tests/test-plo.c | 8 +++--- memcheck/tests/unit_oset.c | 11 ++++---- none/tests/mips64/change_fp_mode.c | 13 ++++----- none/tests/mips64/const.h | 2 +- none/tests/mips64/cvm_bbit.c | 8 +++--- none/tests/mips64/cvm_ins.c | 19 +++++++------- none/tests/mips64/fpu_load_store.c | 1 + none/tests/mips64/load_store.c | 1 + none/tests/mips64/macro_load_store.h | 38 +++++++++++++++------------ none/tests/mips64/move_instructions.c | 4 +-- none/tests/mips64/round.c | 4 +-- none/tests/mips64/test_fcsr.c | 7 ++--- 14 files changed, 77 insertions(+), 68 deletions(-) diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c index 74cf9d86c7..e311714f76 100644 --- a/helgrind/tests/annotate_hbefore.c +++ b/helgrind/tests/annotate_hbefore.c @@ -219,7 +219,7 @@ UWord do_acasW(UWord* addr, UWord expected, UWord nyu ) return cc == 0; } -#elif defined(VGA_mips32) +#elif defined(VGA_mips32) || (defined(VGA_mips64) && defined(VGABI_N32)) // mips32 /* return 1 if success, 0 if failure */ @@ -252,7 +252,7 @@ UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) return success; } -#elif defined(VGA_mips64) +#elif defined(VGA_mips64) && !defined(VGABI_N32) // mips64 /* return 1 if success, 0 if failure */ diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c index 1fede8c8f5..b6816d78a7 100644 --- a/memcheck/tests/atomic_incs.c +++ b/memcheck/tests/atomic_incs.c @@ -17,6 +17,7 @@ #include #include #include "tests/sys_mman.h" +#include "pub_core_basics.h" #define NNN 3456987 @@ -193,8 +194,8 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) /* We rely on the fact that p is 4-aligned. Otherwise 'll' may throw an exception that can cause this function to fail. */ #if defined (_MIPSEL) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n, 0x0ULL }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n, 0x0ULL }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" @@ -216,8 +217,8 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) ); } while (block[2] != 1); #elif defined (_MIPSEB) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n << 56, 0x0 }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n << 56, 0x0 }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" @@ -409,8 +410,8 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n ) /* We rely on the fact that p is 4-aligned. Otherwise 'll' may throw an exception that can cause this function to fail. */ #if defined (_MIPSEL) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n, 0x0ULL }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n, 0x0ULL }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" @@ -432,8 +433,8 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n ) ); } while (block[2] != 1); #elif defined (_MIPSEB) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n << 48, 0x0 }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n << 48, 0x0 }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" @@ -588,8 +589,8 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n ) ); } while (block[2] != 1); #elif defined(VGA_mips64) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n, 0x0ULL }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n, 0x0ULL }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" @@ -689,8 +690,8 @@ __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n ) : "d" (n) : "cc", "memory", "0", "1"); #elif defined(VGA_mips64) - unsigned long block[3] - = { (unsigned long)p, (unsigned long)n, 0x0ULL }; + RegWord block[3] + = { (RegWord)(Addr)p, (RegWord)n, 0x0ULL }; do { __asm__ __volatile__( "move $t0, %0" "\n\t" diff --git a/memcheck/tests/test-plo.c b/memcheck/tests/test-plo.c index 5d4da6b9f3..f1f93726bf 100644 --- a/memcheck/tests/test-plo.c +++ b/memcheck/tests/test-plo.c @@ -1,10 +1,8 @@ #include "tests/malloc.h" +#include "pub_core_basics.h" #include #include -typedef unsigned long long int ULong; -typedef unsigned long int UWord; - __attribute__((noinline)) static int my_ffsll ( ULong x ) { @@ -70,11 +68,11 @@ main(int argc, char *argv[]) word-sized load gives an addressing error regardless of the start of --partial-loads-ok=. *And* that the resulting value is completely defined. */ - UWord* words = malloc(3 * sizeof(UWord)); + RegWord* words = malloc(3 * sizeof(RegWord)); free(words); /* Should ALWAYS give an addr error. */ - UWord w = words[1]; + RegWord w = words[1]; /* Should NEVER give an error (you might expect a value one, but no.) */ if (w == 0x31415927) { diff --git a/memcheck/tests/unit_oset.c b/memcheck/tests/unit_oset.c index ff93398ae8..1d2d255610 100644 --- a/memcheck/tests/unit_oset.c +++ b/memcheck/tests/unit_oset.c @@ -434,8 +434,8 @@ void example1b(void) typedef struct { Int b1; - Addr first; - Addr last; + RegWord first; + RegWord last; Int b2; } Block; @@ -445,13 +445,14 @@ static HChar *blockToStr(void *p) { static HChar buf[32]; Block* b = (Block*)p; - sprintf(buf, "<(%d) %lu..%lu (%d)>", b->b1, b->first, b->last, b->b2); + sprintf(buf, "<(%d) %" FMT_REGWORD "u..%" FMT_REGWORD "u (%d)>", + b->b1, b->first, b->last, b->b2); return buf; } static Word blockCmp(const void* vkey, const void* velem) { - Addr key = *(const Addr*)vkey; + RegWord key = *(const RegWord*)vkey; const Block* elem = (const Block*)velem; assert(elem->first <= elem->last); @@ -463,7 +464,7 @@ static Word blockCmp(const void* vkey, const void* velem) void example2(void) { Int i, n; - Addr a; + RegWord a; Block* vs[NN]; Block v, prev; Block *pv; diff --git a/none/tests/mips64/change_fp_mode.c b/none/tests/mips64/change_fp_mode.c index 67cb72de01..4dca120afc 100644 --- a/none/tests/mips64/change_fp_mode.c +++ b/none/tests/mips64/change_fp_mode.c @@ -4,6 +4,7 @@ #include #include #include +#include "pub_core_basics.h" #if !defined(PR_SET_FP_MODE) # define PR_SET_FP_MODE 45 @@ -51,9 +52,9 @@ #define TEST_ST64(instruction) \ { \ - unsigned long result; \ + RegWord result; \ _TEST_ST(instruction); \ - printf(instruction" :: mem: %lx\n", result); \ + printf(instruction" :: mem: %" FMT_REGWORD "x\n", result); \ } #define TEST_ST32(instruction) \ @@ -86,7 +87,7 @@ #define TEST_MF(instruction) \ { \ - unsigned long result; \ + RegWord result; \ __asm__ volatile( \ ".set push\n\t" \ ".set noreorder\n\t" \ @@ -100,7 +101,7 @@ : "=m" (result) \ : "m" (source64) \ : "t0", "$f0", "$f1"); \ - printf(instruction" :: t0: %lx\n", result); \ + printf(instruction" :: t0: %" FMT_REGWORD "x\n", result); \ } #define TEST_MOVE(instruction) \ @@ -127,13 +128,13 @@ result2, result1); \ } -unsigned long source64 = 0x1234567890abcdefull; +ULong source64 = 0x1234567890abcdefull; unsigned int source32 = 0x12345678u; /* Determine FP mode based on sdc1 behavior returns 1 if FR = 1 mode is detected (assumes FRE = 0) */ static int get_fp_mode(void) { - unsigned long result = 0; + unsigned long long result = 0; __asm__ volatile( ".set push\n\t" ".set noreorder\n\t" diff --git a/none/tests/mips64/const.h b/none/tests/mips64/const.h index 5ccab70e98..fa4e88b25e 100644 --- a/none/tests/mips64/const.h +++ b/none/tests/mips64/const.h @@ -157,7 +157,7 @@ const int fs_w[] = { -347856, 0x80000000, 0xfffffff, 23, }; -const long fs_l[] = { +const long long fs_l[] = { 18, 25, 3, -1, 0xffffffff, 356, 1000000, -5786, -1, 24575, 10, -125458, diff --git a/none/tests/mips64/cvm_bbit.c b/none/tests/mips64/cvm_bbit.c index b1966b9111..1f94bea907 100644 --- a/none/tests/mips64/cvm_bbit.c +++ b/none/tests/mips64/cvm_bbit.c @@ -33,10 +33,10 @@ int main() printf("TEST bbit0: %s\n", t1 == 0x08 ? "PASS" : "FAIL"); printf("TEST bbit1: %s\n", t2 == 0xF7 ? "PASS" : "FAIL"); - long int lt1 = 0; - long int lt2 = 0; - long int lt3 = 0xff00000000; - long int lt4 = 0x100000000; + long long int lt1 = 0; + long long int lt2 = 0; + long long int lt3 = 0xff00000000; + long long int lt4 = 0x100000000; /* Take 0x100000000 and loop until 35th bit is set by incrementing 0x100000000 at a time. */ __asm__ volatile( diff --git a/none/tests/mips64/cvm_ins.c b/none/tests/mips64/cvm_ins.c index fee6f901b4..3d7a7c237b 100644 --- a/none/tests/mips64/cvm_ins.c +++ b/none/tests/mips64/cvm_ins.c @@ -1,4 +1,5 @@ #include +#include "pub_core_basics.h" const int reg_val[256] = { 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L, @@ -69,7 +70,7 @@ const int reg_val[256] = { #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \ { \ - unsigned long out; \ + RegWord out; \ __asm__ volatile( \ "li $" #RT ", 0" "\n\t" \ "move $" #RS ", %1" "\n\t" \ @@ -79,12 +80,12 @@ const int reg_val[256] = { : "r" (RSVal) \ : #RS, #RT, "cc", "memory" \ ); \ - printf("%s :: rt 0x%lx rs 0x%x, p 0x%08x, lenm1 0x%08x\n", \ - instruction, out, RSVal, p, lenm1); \ + printf("%s :: rt 0x%" FMT_REGWORD "x rs 0x%x, p 0x%08x, " \ + "lenm1 0x%08x\n", instruction, out, RSVal, p, lenm1); \ } #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ { \ - unsigned long out; \ + RegWord out; \ __asm__ volatile( \ "li $" #RD ", 0" "\n\t" \ "move $" #RS ", %1" "\n\t" \ @@ -95,12 +96,12 @@ const int reg_val[256] = { : "r" (RSVal), "r" (RTval) \ : #RD, #RS, #RT, "cc", "memory" \ ); \ - printf("%s :: rd 0x%lx rs 0x%x, rt 0x%x\n", \ - instruction, out, RSVal, RTval); \ + printf("%s :: rd 0x%" FMT_REGWORD "x rs 0x%x, " \ + "rt 0x%x\n", instruction, out, RSVal, RTval); \ } #define TESTINST3(instruction, RSVal, RT, RS, imm) \ { \ - unsigned long out; \ + RegWord out; \ __asm__ volatile( \ "li $" #RT ", 0" "\n\t" \ "move $" #RS ", %1" "\n\t" \ @@ -110,8 +111,8 @@ const int reg_val[256] = { : "r" (RSVal) \ : #RS, #RT, "cc", "memory" \ ); \ - printf("%s :: rt 0x%lx rs 0x%x,imm 0x%08x\n", \ - instruction, out, RSVal, imm); \ + printf("%s :: rt 0x%" FMT_REGWORD "x rs 0x%x,imm " \ + "0x%08x\n", instruction, out, RSVal, imm); \ } typedef enum { diff --git a/none/tests/mips64/fpu_load_store.c b/none/tests/mips64/fpu_load_store.c index 0ad4929ee5..f408ffa2ca 100644 --- a/none/tests/mips64/fpu_load_store.c +++ b/none/tests/mips64/fpu_load_store.c @@ -1,4 +1,5 @@ #include +#include "pub_core_basics.h" #include "macro_load_store.h" int main() diff --git a/none/tests/mips64/load_store.c b/none/tests/mips64/load_store.c index bca86d30b7..704b52c1bb 100644 --- a/none/tests/mips64/load_store.c +++ b/none/tests/mips64/load_store.c @@ -1,4 +1,5 @@ #include +#include "pub_core_basics.h" #include "macro_load_store.h" int main() diff --git a/none/tests/mips64/macro_load_store.h b/none/tests/mips64/macro_load_store.h index 7fb34c6cc8..0575e63f4d 100644 --- a/none/tests/mips64/macro_load_store.h +++ b/none/tests/mips64/macro_load_store.h @@ -2,7 +2,7 @@ #define TEST1(instruction, offset, mem) \ { \ - unsigned long out = 0; \ + RegWord out = 0; \ __asm__ __volatile__( \ "move $t0, %1" "\n\t" \ "move $t1, %2" "\n\t" \ @@ -14,14 +14,15 @@ : "r" (mem), "r" (offset) \ : "t0", "t1" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%lx\n", \ - instruction, offset, out); \ + printf("%s :: offset: 0x%x, out: 0x%" \ + FMT_REGWORD "x\n", instruction, \ + offset, out); \ } #define TEST2(instruction, offset) \ { \ - unsigned long out = 0; \ - unsigned long outHI = 0; \ + RegWord out = 0; \ + RegWord outHI = 0; \ __asm__ __volatile__( \ "move $t0, %2" "\n\t" \ "move $t1, %4" "\n\t" \ @@ -40,13 +41,14 @@ : "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \ : "t0", "t1", "t2", "t3" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%lx, outHI: 0x%lx\n", \ - instruction, offset, out, outHI); \ + printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x, " \ + "outHI: 0x%" FMT_REGWORD "x\n", instruction, \ + offset, out, outHI); \ } #define TEST3(instruction, offset, mem) \ { \ - unsigned long long out = 0; \ + RegWord out = 0; \ __asm__ __volatile__( \ "move $t0, %1" "\n\t" \ "move $t1, %2" "\n\t" \ @@ -58,8 +60,9 @@ : "r" (mem) , "r" (offset) \ : "t0", "t1", "$f0" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%llx\n", \ - instruction, offset, out); \ + printf("%s :: offset: 0x%x, out: 0x%" \ + FMT_REGWORD "x\n", instruction, \ + offset, out); \ } #define TEST3w(instruction, offset, mem) \ @@ -82,7 +85,7 @@ #define TEST4(instruction, offset) \ { \ - unsigned long long out = 0; \ + RegWord out = 0; \ __asm__ __volatile__( \ "move $t0, %1" "\n\t" \ "move $t1, %3" "\n\t" \ @@ -97,13 +100,13 @@ : "r" (reg_val1) , "r" (reg_val_zero), "r" (offset) \ : "t0", "t1", "t2", "$f0" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%llx\n", \ + printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x\n",\ instruction, offset, out); \ } #define TEST5(instruction, offset, mem) \ { \ - unsigned long long out = 0; \ + RegWord out = 0; \ __asm__ __volatile__( \ "move $t0, %1" "\n\t" \ "move $t1, %2" "\n\t" \ @@ -114,8 +117,9 @@ : "r" (mem) , "r" (offset) \ : "t0", "t1", "$f0" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%llx\n", \ - instruction, offset, out); \ + printf("%s :: offset: 0x%x, out: 0x%" \ + FMT_REGWORD "x\n", instruction, \ + offset, out); \ } #define TEST5w(instruction, offset, mem) \ @@ -137,7 +141,7 @@ #define TEST6(instruction, offset) \ { \ - unsigned long long out = 0; \ + RegWord out = 0; \ __asm__ __volatile__( \ "move $t0, %1" "\n\t" \ "move $t1, %3" "\n\t" \ @@ -154,6 +158,6 @@ : "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \ : "t0", "t1", "t2", "t3" \ ); \ - printf("%s :: offset: 0x%x, out: 0x%llx\n", \ + printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x\n",\ instruction, offset, out); \ } diff --git a/none/tests/mips64/move_instructions.c b/none/tests/mips64/move_instructions.c index 566940f099..4ea8255209 100644 --- a/none/tests/mips64/move_instructions.c +++ b/none/tests/mips64/move_instructions.c @@ -179,7 +179,7 @@ const double fs2_f[] = { /* movf, movt */ #define TEST5(instruction, RDval, RSval, RD, RS) \ { \ - unsigned long out; \ + unsigned long long out; \ __asm__ __volatile__( \ "c.eq.s %3, %4" "\n\t" \ "move $"#RD", %1" "\n\t" \ @@ -190,7 +190,7 @@ const double fs2_f[] = { : "r" (RDval), "r" (RSval), "f" (fs1_f[i]), "f" (fs2_f[i]) \ : #RD, #RS \ ); \ - printf("%s :: RDval: 0x%x, RSval: 0x%x, out: 0x%lx\n", \ + printf("%s :: RDval: 0x%x, RSval: 0x%x, out: 0x%llx\n", \ instruction, RDval, RSval, out); \ } #endif diff --git a/none/tests/mips64/round.c b/none/tests/mips64/round.c index 1894de14e6..44be246b70 100644 --- a/none/tests/mips64/round.c +++ b/none/tests/mips64/round.c @@ -157,7 +157,7 @@ int FCSRRoundingMode(flt_round_op_t op1) break; case CVTDL: UNOPld("cvt.d.l"); - printf("%s %lf %ld\n", flt_round_op_names[op1], fd_d, fs_l[i]); + printf("%s %lf %lld\n", flt_round_op_names[op1], fd_d, fs_l[i]); printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr)); break; case CVTLS: @@ -172,7 +172,7 @@ int FCSRRoundingMode(flt_round_op_t op1) break; case CVTSL: UNOPls("cvt.s.l"); - printf("%s %f %ld\n", flt_round_op_names[op1], fd_f, fs_l[i]); + printf("%s %f %lld\n", flt_round_op_names[op1], fd_f, fs_l[i]); printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr)); break; default: diff --git a/none/tests/mips64/test_fcsr.c b/none/tests/mips64/test_fcsr.c index 07e5e8c37c..a99f89e6b6 100644 --- a/none/tests/mips64/test_fcsr.c +++ b/none/tests/mips64/test_fcsr.c @@ -1,4 +1,5 @@ #include +#include "pub_core_basics.h" /* * Bits 18 (NAN2008) and 19 (ABS2008) are preset by hardware and may differ @@ -13,7 +14,7 @@ int main () { #if defined(__mips_hard_float) - long out [] = {0, 0}; + RegWord out [] = {0, 0}; __asm__ volatile("cfc1 $a1, $31" "\n\t" "dli $t0, 0x405ee0a3d70a3d71" "\n\t" "dmtc1 $t0, $f0" "\n\t" @@ -32,8 +33,8 @@ int main () : "r" (out) : "a1", "a2", "t0", "$f0" ); - printf("FCSR::1: 0x%lx, 2: 0x%lx\n", CLEAR_PRESETBITS_FCSR(out[0]), - CLEAR_PRESETBITS_FCSR(out[1])); + printf("FCSR::1: 0x%" FMT_REGWORD "x, 2: 0x%" FMT_REGWORD "x\n", + CLEAR_PRESETBITS_FCSR(out[0]), CLEAR_PRESETBITS_FCSR(out[1])); #endif return 0; } -- 2.47.2