From 5b1fe74facc2abab66cee1d18a74807f457983ff Mon Sep 17 00:00:00 2001 From: "Bastien Curutchet (Schneider Electric)" Date: Mon, 5 Jan 2026 14:08:05 +0100 Subject: [PATCH] net: dsa: microchip: Use regs[] to access REG_PTP_RTC_SUB_NANOSEC Accesses to the PTP_RTC_SUB_NANOSEC register are done through a hardcoded address which doesn't match with the KSZ8463's register layout. Add a new entry for the PTP_RTC_SUB_NANOSEC register in the regs[] tables. Use the regs[] table to retrieve the PTP_RTC_SUB_NANOSEC register address when accessing it. Remove the macro defining the address to prevent further use. Signed-off-by: Bastien Curutchet (Schneider Electric) Link: https://patch.msgid.link/20260105-ksz-rework-v1-6-a68df7f57375@bootlin.com Signed-off-by: Paolo Abeni --- drivers/net/dsa/microchip/ksz_common.c | 2 ++ drivers/net/dsa/microchip/ksz_common.h | 1 + drivers/net/dsa/microchip/ksz_ptp.c | 4 ++-- drivers/net/dsa/microchip/ksz_ptp_reg.h | 3 +-- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 595438031d316..7af008cafccf7 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -572,6 +572,7 @@ static const u16 ksz8463_regs[] = { [PTP_CLK_CTRL] = 0x0600, [PTP_RTC_NANOSEC] = 0x0604, [PTP_RTC_SEC] = 0x0608, + [PTP_RTC_SUB_NANOSEC] = 0x060C, }; static const u32 ksz8463_masks[] = { @@ -807,6 +808,7 @@ static const u16 ksz9477_regs[] = { [REG_PORT_PME_STATUS] = 0x0013, [REG_PORT_PME_CTRL] = 0x0017, [PTP_CLK_CTRL] = 0x0500, + [PTP_RTC_SUB_NANOSEC] = 0x0502, [PTP_RTC_NANOSEC] = 0x0504, [PTP_RTC_SEC] = 0x0508, }; diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index b4305bd47fbeb..d1baa3ce09b5f 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -274,6 +274,7 @@ enum ksz_regs { PTP_CLK_CTRL, PTP_RTC_NANOSEC, PTP_RTC_SEC, + PTP_RTC_SUB_NANOSEC, }; enum ksz_masks { diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 5a94beb410df3..3766d8bde478e 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -596,7 +596,7 @@ static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) if (ret) return ret; - ret = ksz_read8(dev, REG_PTP_RTC_SUB_NANOSEC__2, &phase); + ret = ksz_read8(dev, regs[PTP_RTC_SUB_NANOSEC], &phase); if (ret) return ret; @@ -683,7 +683,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp, mutex_lock(&ptp_data->lock); /* Write to shadow registers and Load PTP clock */ - ret = ksz_write16(dev, REG_PTP_RTC_SUB_NANOSEC__2, PTP_RTC_0NS); + ret = ksz_write16(dev, regs[PTP_RTC_SUB_NANOSEC], PTP_RTC_0NS); if (ret) goto unlock; diff --git a/drivers/net/dsa/microchip/ksz_ptp_reg.h b/drivers/net/dsa/microchip/ksz_ptp_reg.h index d1d3151448860..41891ddadaa30 100644 --- a/drivers/net/dsa/microchip/ksz_ptp_reg.h +++ b/drivers/net/dsa/microchip/ksz_ptp_reg.h @@ -24,8 +24,7 @@ #define PTP_CLK_ENABLE BIT(1) #define PTP_CLK_RESET BIT(0) -#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 - +/* REG_PTP_RTC_SUB_NANOSEC */ #define PTP_RTC_SUB_NANOSEC_M 0x0007 #define PTP_RTC_0NS 0x00 -- 2.47.3