From 5c2586fa59e9f336babfb4b14bdeb6f90ac6cabd Mon Sep 17 00:00:00 2001 From: Venkataramanan Kumar Date: Mon, 8 Jun 2015 10:18:02 +0000 Subject: [PATCH] sse.md (sse3_mwait): Swap the operand constriants. 2015-06-08 Venkataramanan Kumar * config/i386/sse.md (sse3_mwait): Swap the operand constriants. From-SVN: r224214 --- gcc/ChangeLog | 4 ++++ gcc/config/i386/sse.md | 8 +++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 512d82789ee7..09dbbcb45825 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2015-06-08 Venkataramanan Kumar + + * config/i386/sse.md (sse3_mwait): Swap the operand constriants. + 2015-06-03 Jakub Jelinek Backported from mainline diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5973b3423b05..8f5120f2ef73 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10837,10 +10837,12 @@ (set_attr "atom_sse_attr" "fence") (set_attr "memory" "unknown")]) - +;; As per AMD and Intel ISA manuals, the first operand is extensions +;; and it goes to %ecx. The second operand received is hints and it goes +;; to %eax. (define_insn "sse3_mwait" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c")] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "c") + (match_operand:SI 1 "register_operand" "a")] UNSPECV_MWAIT)] "TARGET_SSE3" ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used. -- 2.47.2