From 601a412ef0fe59ce48fb8635ebdaa58b58512a5a Mon Sep 17 00:00:00 2001
From: Die Li <lidie@eswincomputing.com>
Date: Fri, 14 Jul 2023 02:02:05 +0000
Subject: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3.

When generating the gen_and<mode>3 function based on the and<mode>3
template, it produces the expression emit_insn (gen_rtx_SET (operand0,
gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the
portion I removed in this patch. Therefore, the redundant portion can be
deleted.

Signed-off-by: Die Li <lidie@eswincomputing.com>

gcc/ChangeLog:

	* config/riscv/riscv.md: Remove redundant portion in and<mode>3.
---
 gcc/config/riscv/riscv.md | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7988026d1294..c4f8eb9488e9 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1491,11 +1491,6 @@
 	  DONE;
 	}
     }
-  else
-    {
-      emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2]));
-      DONE;
-    }
 })
 
 (define_insn "*and<mode>3"
-- 
2.47.2