From 626fb1be7237bdc4190cad8b500c5a897b9f26a9 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Fri, 14 Feb 2014 17:28:15 +0000 Subject: [PATCH] mips64: add support for load indexed instructions from DSP ASE Handling lwx, ldx and lbux for MIPS-Cavium processors. Patch by Zahid Anwar, with some changes. Related to Bugzilla issue 326444. git-svn-id: svn://svn.valgrind.org/vex/trunk@2819 --- VEX/priv/guest_mips_toIR.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index 15c4e304cc..9ee65bf434 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -2278,6 +2278,31 @@ static Bool dis_instr_CVM ( UInt theInstr ) switch(opc2) { case 0x0A: { // lx - Load indexed instructions switch (get_sa(theInstr)) { + case 0x00: { // LWX rd, index(base) + DIP("lwx r%d, r%d(r%d)", regRd, regRt, regRs); + LOADX_STORE_PATTERN; + putIReg(regRd, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), + True)); + break; + } + case 0x08: { // LDX rd, index(base) + DIP("ldx r%d, r%d(r%d)", regRd, regRt, regRs); + vassert(mode64); /* Currently Implemented only for n64 */ + LOADX_STORE_PATTERN; + putIReg(regRd, load(Ity_I64, mkexpr(t1))); + break; + } + case 0x06: { // LBUX rd, index(base) + DIP("lbux r%d, r%d(r%d)", regRd, regRt, regRs); + LOADX_STORE_PATTERN; + if (mode64) + putIReg(regRd, unop(Iop_8Uto64, load(Ity_I8, + mkexpr(t1)))); + else + putIReg(regRd, unop(Iop_8Uto32, load(Ity_I8, + mkexpr(t1)))); + break; + } case 0x10: { // LWUX rd, index(base) (Cavium OCTEON) DIP("lwux r%d, r%d(r%d)", regRd, regRt, regRs); LOADX_STORE_PATTERN; /* same for both 32 and 64 modes*/ -- 2.47.2