From 62b7052ab529d02b5852b547bfac6c6547a944e9 Mon Sep 17 00:00:00 2001 From: Andreas Arnez Date: Mon, 17 May 2021 15:34:15 +0200 Subject: [PATCH] s390x: Vec-enh-2, test cases Add test cases for verifying the new/enhanced instructions in the vector-enhancements facility 2. For "vector string search" VSTRS add a memcheck test case. --- .gitignore | 2 + memcheck/tests/s390x/Makefile.am | 3 +- memcheck/tests/s390x/vstrs.c | 68 ++++++ memcheck/tests/s390x/vstrs.stderr.exp | 16 ++ memcheck/tests/s390x/vstrs.stdout.exp | 0 memcheck/tests/s390x/vstrs.vgtest | 2 + none/tests/s390x/Makefile.am | 3 +- none/tests/s390x/vec2.c | 314 ++++++++++++++++++++++++++ none/tests/s390x/vec2.stderr.exp | 2 + none/tests/s390x/vec2.stdout.exp | 168 ++++++++++++++ none/tests/s390x/vec2.vgtest | 2 + tests/s390x_features.c | 4 + 12 files changed, 582 insertions(+), 2 deletions(-) create mode 100644 memcheck/tests/s390x/vstrs.c create mode 100644 memcheck/tests/s390x/vstrs.stderr.exp create mode 100644 memcheck/tests/s390x/vstrs.stdout.exp create mode 100644 memcheck/tests/s390x/vstrs.vgtest create mode 100644 none/tests/s390x/vec2.c create mode 100644 none/tests/s390x/vec2.stderr.exp create mode 100644 none/tests/s390x/vec2.stdout.exp create mode 100644 none/tests/s390x/vec2.vgtest diff --git a/.gitignore b/.gitignore index b418f52fdc..cf45901132 100644 --- a/.gitignore +++ b/.gitignore @@ -1121,6 +1121,7 @@ /memcheck/tests/s390x/vstrc /memcheck/tests/s390x/vfae /memcheck/tests/s390x/vistr +/memcheck/tests/s390x/vstrs # /memcheck/tests/solaris/ /memcheck/tests/solaris/*.stderr.diff @@ -1888,6 +1889,7 @@ /none/tests/s390x/high-word /none/tests/s390x/vector_float /none/tests/s390x/misc3 +/none/tests/s390x/vec2 # /none/tests/scripts/ /none/tests/scripts/*.dSYM diff --git a/memcheck/tests/s390x/Makefile.am b/memcheck/tests/s390x/Makefile.am index d183841ef0..668fd9933c 100644 --- a/memcheck/tests/s390x/Makefile.am +++ b/memcheck/tests/s390x/Makefile.am @@ -2,7 +2,7 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = filter_stderr -INSN_TESTS = cdsg cu21 cu42 ltgjhe vstrc vfae vistr +INSN_TESTS = cdsg cu21 cu42 ltgjhe vstrc vfae vistr vstrs check_PROGRAMS = $(INSN_TESTS) @@ -18,3 +18,4 @@ AM_CCASFLAGS += @FLAG_M64@ vstrc_CFLAGS = $(AM_CFLAGS) -march=z13 vfae_CFLAGS = $(AM_CFLAGS) -march=z13 vistr_CFLAGS = $(AM_CFLAGS) -march=z13 +vstrs_CFLAGS = $(AM_CFLAGS) -march=z13 diff --git a/memcheck/tests/s390x/vstrs.c b/memcheck/tests/s390x/vstrs.c new file mode 100644 index 0000000000..3354c2e538 --- /dev/null +++ b/memcheck/tests/s390x/vstrs.c @@ -0,0 +1,68 @@ +#include +#include + +#define VECTOR __attribute__ ((vector_size (16))) + +typedef char VECTOR char_v; + +volatile char tmp; +static const char *hex_digit = "0123456789abcdefGHIJKLMNOPQRSTUV"; + +static char_v to_char_vec(const char *str) +{ + char buf[17]; + char_v v; + + for (int i = 0; i < sizeof(buf); i++) { + char ch = str[i]; + if (ch == '\0') + break; + else if (ch == '$') + buf[i] = '\0'; + else if (ch != '~') + buf[i] = ch; + } + v = *(char_v *) buf; + return v; +} + +static void test_vstrs_char(const char *haystack, const char *needle, + int expect_res, int expect_cc) +{ + int cc; + char_v v2val = to_char_vec(haystack); + char_v v3val = to_char_vec(needle); + + register unsigned long VECTOR v4 __asm__("v4") = { strlen(needle), 0 }; + register char_v v1 __asm__("v1"); + register char_v v2 __asm__("v2") = v2val; + register char_v v3 __asm__("v3") = v3val; + + __asm__( + "cr 0,0\n\t" /* Clear CC */ + ".short 0xe712,0x3020,0x408b\n\t" /* vstrs %v1,%v2,%v3,%v4,0,2 */ + "ipm %[cc]\n\t" + "srl %[cc],28" + : "=v" (v1), [cc] "=d" (cc) + : "v" (v2), "v" (v3), "v" (v4) + : "cc"); + + tmp = hex_digit[v1[7] & 0x1f]; + if (expect_res >= 0 && v1[7] != expect_res) + printf("result %u != %d\n", v1[7], expect_res); + + tmp = hex_digit[cc & 0xf]; + if (expect_cc >= 0 && cc != expect_cc) + printf("CC %d != %d\n", cc, expect_cc); +} + +int main() +{ + test_vstrs_char("haystack$needle", "needle$haystack", 16, 1); + test_vstrs_char("haystack, needle", "needle, haystack", 10, 3); + test_vstrs_char("ABCDEFGH", "DEFGHI", -1, -1); + test_vstrs_char("match in UNDEF", "UN", 9, 2); + test_vstrs_char("after ~ UNDEF", "DEF", -1, -1); + test_vstrs_char("", "", 0, 2); + return 0; +} diff --git a/memcheck/tests/s390x/vstrs.stderr.exp b/memcheck/tests/s390x/vstrs.stderr.exp new file mode 100644 index 0000000000..c5c3ef705c --- /dev/null +++ b/memcheck/tests/s390x/vstrs.stderr.exp @@ -0,0 +1,16 @@ +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:50) + by 0x........: main (vstrs.c:63) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:54) + by 0x........: main (vstrs.c:63) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:50) + by 0x........: main (vstrs.c:65) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:54) + by 0x........: main (vstrs.c:65) + diff --git a/memcheck/tests/s390x/vstrs.stdout.exp b/memcheck/tests/s390x/vstrs.stdout.exp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/memcheck/tests/s390x/vstrs.vgtest b/memcheck/tests/s390x/vstrs.vgtest new file mode 100644 index 0000000000..fd2a298739 --- /dev/null +++ b/memcheck/tests/s390x/vstrs.vgtest @@ -0,0 +1,2 @@ +prog: vstrs +vgopts: -q diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index 2fd45ec1e8..ca38db935c 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -20,7 +20,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \ spechelper-icm-1 spechelper-icm-2 spechelper-tmll \ spechelper-tm laa vector lsc2 ppno vector_string vector_integer \ vector_float add-z14 sub-z14 mul-z14 bic \ - misc3 + misc3 vec2 if BUILD_DFP_TESTS INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo @@ -74,3 +74,4 @@ lsc2_CFLAGS = -march=z13 -DS390_TESTS_NOCOLOR vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5 vector_integer_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 vector_float_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 +vec2_CFLAGS = $(AM_CFLAGS) -march=z13 diff --git a/none/tests/s390x/vec2.c b/none/tests/s390x/vec2.c new file mode 100644 index 0000000000..73b04dee49 --- /dev/null +++ b/none/tests/s390x/vec2.c @@ -0,0 +1,314 @@ +#include + +#define VECTOR __attribute__ ((vector_size (16))) + +typedef unsigned long VECTOR ulong_v; +typedef float VECTOR float_v; + +static const ulong_v vec_a = { 0x0123456789abcdef, 0xfedcba9876543210 }; +static const ulong_v vec_b = { 0xfedcba9876543210, 0x0123456789abcdef }; +static const ulong_v vec_c = { 0x8040201008040201, 0x7fbfdfeff7fbfdfe }; +static const ulong_v vec_one = { -1, -1 }; +static const ulong_v vec_ini = { 0x0112233445566778, 0x899aabbccddeeff0 }; + +static const float_v vec_fa = { 16777215., -16777215., 42.5, 10000. }; +static const float_v vec_fb = { 4., 3., 2., 1. }; + +/* -- Vector shift -- */ + +#define TEST_GENERATE(insn) \ + static void test_##insn(ulong_v a, ulong_v b) \ + { \ + ulong_v out; \ + __asm__( \ + #insn " %[out],%[a],%[b]" \ + : [out] "=v" (out) \ + : [a] "v" (a), \ + [b] "v" (b) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define TEST_EXEC(insn) \ + do { \ + puts(#insn); \ + test_##insn(vec_a, vec_b); \ + test_##insn(vec_b, vec_a); \ + test_##insn(vec_c, vec_a); \ + test_##insn(vec_one, vec_b); \ + } while (0) + +#define INSNS \ + XTEST(vsl); \ + XTEST(vsrl); \ + XTEST(vsra); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_single_bitshifts() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector load element-/byte-swapped -- */ + +#define TEST_EXEC(opc1,opc2,insn,m3) \ + do { \ + puts(#insn " " #m3); \ + test_##insn##_##m3(vec_a); \ + test_##insn##_##m3(vec_b); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,insn,m3) \ + static void test_##insn##_##m3(ulong_v a) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrx,0x" #opc1 "00000000" #opc2 ",%[out],%[a]," #m3 \ + : [out] "+v" (out) \ + : [a] "R" (a) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define INSNS \ + XTEST(e6,01, vlebrh, 0); \ + XTEST(e6,01, vlebrh, 7); \ + XTEST(e6,01, vlebrh, 2); \ + XTEST(e6,03, vlebrf, 0); \ + XTEST(e6,03, vlebrf, 3); \ + XTEST(e6,03, vlebrf, 1); \ + XTEST(e6,02, vlebrg, 0); \ + XTEST(e6,02, vlebrg, 1); \ + XTEST(e6,04, vllebrz, 1); \ + XTEST(e6,04, vllebrz, 2); \ + XTEST(e6,04, vllebrz, 3); \ + XTEST(e6,04, vllebrz, 6); \ + XTEST(e6,05, vlbrrep, 1); \ + XTEST(e6,05, vlbrrep, 2); \ + XTEST(e6,05, vlbrrep, 3); \ + XTEST(e6,06, vlbr, 1); \ + XTEST(e6,06, vlbr, 2); \ + XTEST(e6,06, vlbr, 3); \ + XTEST(e6,06, vlbr, 4); \ + XTEST(e6,07, vler, 1); \ + XTEST(e6,07, vler, 2); \ + XTEST(e6,07, vler, 3); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_swapped_loads() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE + +/* -- Vector store element-/byte-swapped -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m3) \ + static void test_##insn##_##m3(ulong_v a) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrx,0x" #opc1 "00000000" #opc2 ",%[a],%[out]," #m3 \ + : [out] "+R" (out) \ + : [a] "v" (a) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define INSNS \ + XTEST(e6,09, vstebrh, 0); \ + XTEST(e6,09, vstebrh, 7); \ + XTEST(e6,09, vstebrh, 2); \ + XTEST(e6,0b, vstebrf, 0); \ + XTEST(e6,0b, vstebrf, 3); \ + XTEST(e6,0b, vstebrf, 1); \ + XTEST(e6,0a, vstebrg, 0); \ + XTEST(e6,0a, vstebrg, 1); \ + XTEST(e6,0e, vstbr, 1); \ + XTEST(e6,0e, vstbr, 2); \ + XTEST(e6,0e, vstbr, 3); \ + XTEST(e6,0e, vstbr, 4); \ + XTEST(e6,0f, vster, 1); \ + XTEST(e6,0f, vster, 2); \ + XTEST(e6,0f, vster, 3); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_swapped_stores() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector shift double by bit -- */ + +#define TEST_GENERATE(opc1,opc2,insn,i4) \ + static void test_##insn##_##i4(ulong_v a, ulong_v b) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],%[b],0," #i4 ",0" \ + : [out] "+v" (out) \ + : [a] "v" (a), \ + [b] "v" (b) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,i4) \ + do { \ + puts(#insn " " #i4); \ + test_##insn##_##i4(vec_a, vec_one); \ + test_##insn##_##i4(vec_b, vec_a); \ + } while (0) + +#define INSNS \ + XTEST(e7,86,vsld,0); \ + XTEST(e7,86,vsld,7); \ + XTEST(e7,86,vsld,4); \ + XTEST(e7,87,vsrd,0); \ + XTEST(e7,87,vsrd,7); \ + XTEST(e7,87,vsrd,4); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_double_bitshifts() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector integer -> FP conversions -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m4) \ + static void test_##insn##_##m4(ulong_v a) \ + { \ + float_v out; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],0,2," #m4 ",0" \ + : [out] "=v" (out) \ + : [a] "v" (a) \ + : ); \ + if (m4 & 8) \ + printf("\t%a - - -\n", out[0]); \ + else \ + printf("\t%a %a %a %a\n", out[0], out[1], out[2], out[3]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,m4) \ + do { \ + puts(#insn " " #m4); \ + test_##insn##_##m4(vec_a); \ + test_##insn##_##m4(vec_c); \ + } while (0) + +#define INSNS \ + XTEST(e7,c1,vcfpl,0); \ + XTEST(e7,c1,vcfpl,8); \ + XTEST(e7,c3,vcfps,0); \ + XTEST(e7,c3,vcfps,8); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_int_fp_conversions() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector FP -> integer conversions -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m4) \ + static void test_##insn##_##m4(float_v a) \ + { \ + unsigned int VECTOR out; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],0,2," #m4 ",0" \ + : [out] "=v" (out) \ + : [a] "v" (a) \ + : ); \ + if (m4 & 8) \ + printf("\t%08x - - -\n", out[0]); \ + else \ + printf("\t%08x %08x %08x %08x\n", \ + out[0], out[1], out[2], out[3]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,m4) \ + do { \ + puts(#insn " " #m4); \ + test_##insn##_##m4(vec_fa); \ + test_##insn##_##m4(vec_fb); \ + } while (0) + +#define INSNS \ + XTEST(e7,c0,vclfp,0); \ + XTEST(e7,c0,vclfp,8); \ + XTEST(e7,c2,vcsfp,0); \ + XTEST(e7,c2,vcsfp,8); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_fp_int_conversions() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + + +int main() +{ + test_all_single_bitshifts(); + test_all_swapped_loads(); + test_all_swapped_stores(); + test_all_double_bitshifts(); + test_all_int_fp_conversions(); + test_all_fp_int_conversions(); + return 0; +} diff --git a/none/tests/s390x/vec2.stderr.exp b/none/tests/s390x/vec2.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/s390x/vec2.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/vec2.stdout.exp b/none/tests/s390x/vec2.stdout.exp new file mode 100644 index 0000000000..b32cbe1bc0 --- /dev/null +++ b/none/tests/s390x/vec2.stdout.exp @@ -0,0 +1,168 @@ +vsl + 483415676abc37ef fde5533beca14200 + fde5533beca14200 483415676abc37ef + 00010204102040bf effd7feffebff7fe + ffffffffffffffff ffffffffffffff80 +vsrl + 0012d1679e9af3ef ffdbe5753bcaa164 + 7fdbe5753bcaa164 4012d1679e9af3ef + 4008014004002004 05fbf7efbf7ffffe + 03ffffffffffffff ffffffffffffffff +vsra + 0012d1679e9af3ef ffdbe5753bcaa164 + ffdbe5753bcaa164 4012d1679e9af3ef + c008014004002004 05fbf7efbf7ffffe + ffffffffffffffff ffffffffffffffff +vlebrh 0 + 2301233445566778 899aabbccddeeff0 + dcfe233445566778 899aabbccddeeff0 +vlebrh 7 + 0112233445566778 899aabbccdde2301 + 0112233445566778 899aabbccddedcfe +vlebrh 2 + 0112233423016778 899aabbccddeeff0 + 01122334dcfe6778 899aabbccddeeff0 +vlebrf 0 + 6745230145566778 899aabbccddeeff0 + 98badcfe45566778 899aabbccddeeff0 +vlebrf 3 + 0112233445566778 899aabbc67452301 + 0112233445566778 899aabbc98badcfe +vlebrf 1 + 0112233467452301 899aabbccddeeff0 + 0112233498badcfe 899aabbccddeeff0 +vlebrg 0 + efcdab8967452301 899aabbccddeeff0 + 1032547698badcfe 899aabbccddeeff0 +vlebrg 1 + 0112233445566778 efcdab8967452301 + 0112233445566778 1032547698badcfe +vllebrz 1 + 0000000000002301 0000000000000000 + 000000000000dcfe 0000000000000000 +vllebrz 2 + 0000000067452301 0000000000000000 + 0000000098badcfe 0000000000000000 +vllebrz 3 + efcdab8967452301 0000000000000000 + 1032547698badcfe 0000000000000000 +vllebrz 6 + 6745230100000000 0000000000000000 + 98badcfe00000000 0000000000000000 +vlbrrep 1 + 2301230123012301 2301230123012301 + dcfedcfedcfedcfe dcfedcfedcfedcfe +vlbrrep 2 + 6745230167452301 6745230167452301 + 98badcfe98badcfe 98badcfe98badcfe +vlbrrep 3 + efcdab8967452301 efcdab8967452301 + 1032547698badcfe 1032547698badcfe +vlbr 1 + 23016745ab89efcd dcfe98ba54761032 + dcfe98ba54761032 23016745ab89efcd +vlbr 2 + 67452301efcdab89 98badcfe10325476 + 98badcfe10325476 67452301efcdab89 +vlbr 3 + efcdab8967452301 1032547698badcfe + 1032547698badcfe efcdab8967452301 +vlbr 4 + 1032547698badcfe efcdab8967452301 + efcdab8967452301 1032547698badcfe +vler 1 + 32107654ba98fedc cdef89ab45670123 + cdef89ab45670123 32107654ba98fedc +vler 2 + 76543210fedcba98 89abcdef01234567 + 89abcdef01234567 76543210fedcba98 +vler 3 + fedcba9876543210 0123456789abcdef + 0123456789abcdef fedcba9876543210 +vstebrh 0 + 2301233445566778 899aabbccddeeff0 + dcfe233445566778 899aabbccddeeff0 +vstebrh 7 + 1032233445566778 899aabbccddeeff0 + efcd233445566778 899aabbccddeeff0 +vstebrh 2 + ab89233445566778 899aabbccddeeff0 + 5476233445566778 899aabbccddeeff0 +vstebrf 0 + 6745230145566778 899aabbccddeeff0 + 98badcfe45566778 899aabbccddeeff0 +vstebrf 3 + 1032547645566778 899aabbccddeeff0 + efcdab8945566778 899aabbccddeeff0 +vstebrf 1 + efcdab8945566778 899aabbccddeeff0 + 1032547645566778 899aabbccddeeff0 +vstebrg 0 + efcdab8967452301 899aabbccddeeff0 + 1032547698badcfe 899aabbccddeeff0 +vstebrg 1 + 1032547698badcfe 899aabbccddeeff0 + efcdab8967452301 899aabbccddeeff0 +vstbr 1 + 23016745ab89efcd dcfe98ba54761032 + dcfe98ba54761032 23016745ab89efcd +vstbr 2 + 67452301efcdab89 98badcfe10325476 + 98badcfe10325476 67452301efcdab89 +vstbr 3 + efcdab8967452301 1032547698badcfe + 1032547698badcfe efcdab8967452301 +vstbr 4 + 1032547698badcfe efcdab8967452301 + efcdab8967452301 1032547698badcfe +vster 1 + 32107654ba98fedc cdef89ab45670123 + cdef89ab45670123 32107654ba98fedc +vster 2 + 76543210fedcba98 89abcdef01234567 + 89abcdef01234567 76543210fedcba98 +vster 3 + fedcba9876543210 0123456789abcdef + 0123456789abcdef fedcba9876543210 +vsld 0 + 0123456789abcdef fedcba9876543210 + fedcba9876543210 0123456789abcdef +vsld 7 + 91a2b3c4d5e6f7ff 6e5d4c3b2a19087f + 6e5d4c3b2a190800 91a2b3c4d5e6f780 +vsld 4 + 123456789abcdeff edcba9876543210f + edcba98765432100 123456789abcdef0 +vsrd 0 + ffffffffffffffff ffffffffffffffff + 0123456789abcdef fedcba9876543210 +vsrd 7 + 21ffffffffffffff ffffffffffffffff + de02468acf13579b dffdb97530eca864 +vsrd 4 + 0fffffffffffffff ffffffffffffffff + f0123456789abcde ffedcba987654321 +vcfpl 0 + 0x1.234568p+24 0x1.13579cp+31 0x1.fdb976p+31 0x1.d950c8p+30 + 0x1.00804p+31 0x1.00804p+27 0x1.feff8p+30 0x1.eff7fcp+31 +vcfpl 8 + 0x1.234568p+24 - - - + 0x1.00804p+31 - - - +vcfps 0 + 0x1.234568p+24 -0x1.d950c8p+30 -0x1.234568p+24 0x1.d950c8p+30 + -0x1.feff8p+30 0x1.00804p+27 0x1.feff8p+30 -0x1.00804p+27 +vcfps 8 + 0x1.234568p+24 - - - + -0x1.feff8p+30 - - - +vclfp 0 + 00ffffff 00000000 0000002a 00002710 + 00000004 00000003 00000002 00000001 +vclfp 8 + 00ffffff - - - + 00000004 - - - +vcsfp 0 + 00ffffff ff000001 0000002a 00002710 + 00000004 00000003 00000002 00000001 +vcsfp 8 + 00ffffff - - - + 00000004 - - - diff --git a/none/tests/s390x/vec2.vgtest b/none/tests/s390x/vec2.vgtest new file mode 100644 index 0000000000..45e942e640 --- /dev/null +++ b/none/tests/s390x/vec2.vgtest @@ -0,0 +1,2 @@ +prog: vec2 +prereq: test -e vec2 && ../../../tests/s390x_features s390x-vx diff --git a/tests/s390x_features.c b/tests/s390x_features.c index 25b98f3a3a..e7939c4635 100644 --- a/tests/s390x_features.c +++ b/tests/s390x_features.c @@ -270,6 +270,10 @@ static int go(char *feature, char *cpu) match = facilities[0] & FAC_BIT(57); /* message security assist 5 facility */ } else if (strcmp(feature, "s390x-mi2") == 0 ) { match = facilities[0] & FAC_BIT(58); + } else if (strcmp(feature, "s390x-mi3") == 0 ) { + match = facilities[0] & FAC_BIT(61); + } else if (strcmp(feature, "s390x-vx2") == 0 ) { + match = facilities[2] & FAC_BIT(20); } else { return 2; // Unrecognised feature. } -- 2.47.2