From 64b9c06d30a34a75913552a944ea87544d820d65 Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Thu, 3 Jul 2014 11:01:38 +0000 Subject: [PATCH] arm32: support (ARM) PLDW [reg, #imm]. The non-W variant was already accepted. Fixes #323179. (vasily.golubev@gmail.com) git-svn-id: svn://svn.valgrind.org/vex/trunk@2896 --- VEX/priv/guest_arm_toIR.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index d1763d3220..c993e4b596 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -14400,13 +14400,14 @@ static Bool decode_NV_instruction ( /*MOD*/DisResult* dres, // Should only be called for NV instructions vassert(BITS4(1,1,1,1) == INSN_COND); - /* ------------------------ pld ------------------------ */ - if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1)) + /* ------------------------ pld{w} ------------------------ */ + if (BITS8(0,1,0,1, 0,0, 0,1) == (INSN(27,20) & BITS8(1,1,1,1, 0,0, 1,1)) && BITS4(1,1,1,1) == INSN(15,12)) { UInt rN = INSN(19,16); UInt imm12 = INSN(11,0); UInt bU = INSN(23,23); - DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12); + UInt bR = INSN(22,22); + DIP("pld%c [r%u, #%c%u]\n", bR ? ' ' : 'w', rN, bU ? '+' : '-', imm12); return True; } -- 2.47.2