From 66be2180e9626c42a2b95262fb2b240c18e39798 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:48 +0800 Subject: [PATCH] arm64: dts: apple: t8011: Add CPU caches Add information about CPU caches in the P-cluster of Apple A10X SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-7-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8011.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 5b280c896b760..974f78cc77cfe 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu1: cpu@1 { @@ -46,6 +49,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu2: cpu@2 { @@ -56,6 +62,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x800000>; /* P-cluster */ }; }; -- 2.47.3