From 6a08718ae54813caddd4d19a22bed36f848d5a8d Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 20 Feb 2023 20:19:35 +0000 Subject: [PATCH] arm: [MVE intrinsics] factorize vcmp Factorize vcmp so that they use the same pattern. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N) (MVE_CMP_M_N_F, mve_cmp_op1): New. (isu): Add VCMP* (supf): Likewise. * config/arm/mve.md (mve_vcmpq_n_): Rename into ... (@mve_vcmpq_n_): ... this. (mve_vcmpeqq_m_f, mve_vcmpgeq_m_f) (mve_vcmpgtq_m_f, mve_vcmpleq_m_f) (mve_vcmpltq_m_f, mve_vcmpneq_m_f): Merge into ... (@mve_vcmpq_m_f): ... this. (mve_vcmpcsq_m_u, mve_vcmpeqq_m_) (mve_vcmpgeq_m_s, mve_vcmpgtq_m_s) (mve_vcmphiq_m_u, mve_vcmpleq_m_s) (mve_vcmpltq_m_s, mve_vcmpneq_m_): Merge into ... (@mve_vcmpq_m_): ... this. (mve_vcmpcsq_m_n_u, mve_vcmpeqq_m_n_) (mve_vcmpgeq_m_n_s, mve_vcmpgtq_m_n_s) (mve_vcmphiq_m_n_u, mve_vcmpleq_m_n_s) (mve_vcmpltq_m_n_s, mve_vcmpneq_m_n_): Merge into ... (@mve_vcmpq_m_n_): ... this. (mve_vcmpeqq_m_n_f, mve_vcmpgeq_m_n_f) (mve_vcmpgtq_m_n_f, mve_vcmpleq_m_n_f) (mve_vcmpltq_m_n_f, mve_vcmpneq_m_n_f): Merge into ... (@mve_vcmpq_m_n_f): ... this. --- gcc/config/arm/iterators.md | 108 ++++++++++ gcc/config/arm/mve.md | 414 +++--------------------------------- 2 files changed, 135 insertions(+), 387 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 3c70fd7f56db..ef9fae0412bc 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -583,6 +583,47 @@ VCREATEQ_F ]) +;; MVE comparison iterators +(define_int_iterator MVE_CMP_M [ + VCMPCSQ_M_U + VCMPEQQ_M_S VCMPEQQ_M_U + VCMPGEQ_M_S + VCMPGTQ_M_S + VCMPHIQ_M_U + VCMPLEQ_M_S + VCMPLTQ_M_S + VCMPNEQ_M_S VCMPNEQ_M_U + ]) + +(define_int_iterator MVE_CMP_M_F [ + VCMPEQQ_M_F + VCMPGEQ_M_F + VCMPGTQ_M_F + VCMPLEQ_M_F + VCMPLTQ_M_F + VCMPNEQ_M_F + ]) + +(define_int_iterator MVE_CMP_M_N [ + VCMPCSQ_M_N_U + VCMPEQQ_M_N_S VCMPEQQ_M_N_U + VCMPGEQ_M_N_S + VCMPGTQ_M_N_S + VCMPHIQ_M_N_U + VCMPLEQ_M_N_S + VCMPLTQ_M_N_S + VCMPNEQ_M_N_S VCMPNEQ_M_N_U + ]) + +(define_int_iterator MVE_CMP_M_N_F [ + VCMPEQQ_M_N_F + VCMPGEQ_M_N_F + VCMPGTQ_M_N_F + VCMPLEQ_M_N_F + VCMPLTQ_M_N_F + VCMPNEQ_M_N_F + ]) + (define_int_iterator MVE_VMAXVQ_VMINVQ [ VMAXAVQ_S VMAXVQ_S VMAXVQ_U @@ -655,6 +696,37 @@ (plus "vadd") ]) +(define_int_attr mve_cmp_op1 [ + (VCMPCSQ_M_U "cs") + (VCMPEQQ_M_S "eq") (VCMPEQQ_M_U "eq") + (VCMPGEQ_M_S "ge") + (VCMPGTQ_M_S "gt") + (VCMPHIQ_M_U "hi") + (VCMPLEQ_M_S "le") + (VCMPLTQ_M_S "lt") + (VCMPNEQ_M_S "ne") (VCMPNEQ_M_U "ne") + (VCMPEQQ_M_F "eq") + (VCMPGEQ_M_F "ge") + (VCMPGTQ_M_F "gt") + (VCMPLEQ_M_F "le") + (VCMPLTQ_M_F "lt") + (VCMPNEQ_M_F "ne") + (VCMPCSQ_M_N_U "cs") + (VCMPEQQ_M_N_S "eq") (VCMPEQQ_M_N_U "eq") + (VCMPGEQ_M_N_S "ge") + (VCMPGTQ_M_N_S "gt") + (VCMPHIQ_M_N_U "hi") + (VCMPLEQ_M_N_S "le") + (VCMPLTQ_M_N_S "lt") + (VCMPNEQ_M_N_S "ne") (VCMPNEQ_M_N_U "ne") + (VCMPEQQ_M_N_F "eq") + (VCMPGEQ_M_N_F "ge") + (VCMPGTQ_M_N_F "gt") + (VCMPLEQ_M_N_F "le") + (VCMPLTQ_M_N_F "lt") + (VCMPNEQ_M_N_F "ne") + ]) + (define_int_attr mve_insn [ (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd") (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd") @@ -836,6 +908,26 @@ (VCLSQ_M_S "s") (VCLZQ_M_S "i") (VCLZQ_M_U "i") + (VCMPCSQ_M_N_U "u") + (VCMPCSQ_M_U "u") + (VCMPEQQ_M_N_S "i") + (VCMPEQQ_M_N_U "i") + (VCMPEQQ_M_S "i") + (VCMPEQQ_M_U "i") + (VCMPGEQ_M_N_S "s") + (VCMPGEQ_M_S "s") + (VCMPGTQ_M_N_S "s") + (VCMPGTQ_M_S "s") + (VCMPHIQ_M_N_U "u") + (VCMPHIQ_M_U "u") + (VCMPLEQ_M_N_S "s") + (VCMPLEQ_M_S "s") + (VCMPLTQ_M_N_S "s") + (VCMPLTQ_M_S "s") + (VCMPNEQ_M_N_S "i") + (VCMPNEQ_M_N_U "i") + (VCMPNEQ_M_S "i") + (VCMPNEQ_M_U "i") (VMOVNBQ_M_S "i") (VMOVNBQ_M_U "i") (VMOVNBQ_S "i") (VMOVNBQ_U "i") (VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i") @@ -2082,6 +2174,22 @@ (VMAXAQ_M_S "s") (VMINAQ_S "s") (VMINAQ_M_S "s") + (VCMPCSQ_M_N_U "u") + (VCMPCSQ_M_U "u") + (VCMPEQQ_M_N_S "s") (VCMPEQQ_M_N_U "u") + (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u") + (VCMPGEQ_M_N_S "s") + (VCMPGEQ_M_S "s") + (VCMPGTQ_M_N_S "s") + (VCMPGTQ_M_S "s") + (VCMPHIQ_M_N_U "u") + (VCMPHIQ_M_U "u") + (VCMPLEQ_M_N_S "s") + (VCMPLEQ_M_S "s") + (VCMPLTQ_M_N_S "s") + (VCMPLTQ_M_S "s") + (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") + (VCMPNEQ_M_S "s") (VCMPNEQ_M_U "u") ]) ;; Both kinds of return insn. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 45bca6d6215a..191d1268ad63 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -695,7 +695,7 @@ ;; ;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_]) ;; -(define_insn "mve_vcmpq_n_" +(define_insn "@mve_vcmpq_n_" [ (set (match_operand: 0 "vpr_register_operand" "=Up") (MVE_COMPARISONS: @@ -1766,18 +1766,23 @@ ]) ;; -;; [vcmpeqq_m_f]) +;; [vcmpeqq_m_f] +;; [vcmpgeq_m_f] +;; [vcmpgtq_m_f] +;; [vcmpleq_m_f] +;; [vcmpltq_m_f] +;; [vcmpneq_m_f] ;; -(define_insn "mve_vcmpeqq_m_f" +(define_insn "@mve_vcmpq_m_f" [ (set (match_operand: 0 "vpr_register_operand" "=Up") (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VCMPEQQ_M_F)) + MVE_CMP_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# eq, %q1, %q2" + "vpst\;vcmpt.f%#\t, %q1, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1954,257 +1959,47 @@ ;; ;; [vcmpcsq_m_n_u]) -;; -(define_insn "mve_vcmpcsq_m_n_u" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPCSQ_M_N_U)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.u%# cs, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpcsq_m_u]) -;; -(define_insn "mve_vcmpcsq_m_u" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPCSQ_M_U)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.u%# cs, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s]) -;; -(define_insn "mve_vcmpeqq_m_n_" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPEQQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.i%# eq, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpeqq_m_u, vcmpeqq_m_s]) -;; -(define_insn "mve_vcmpeqq_m_" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPEQQ_M)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.i%# eq, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpgeq_m_n_s]) -;; -(define_insn "mve_vcmpgeq_m_n_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGEQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# ge, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpgeq_m_s]) -;; -(define_insn "mve_vcmpgeq_m_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGEQ_M_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# ge, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpgtq_m_n_s]) -;; -(define_insn "mve_vcmpgtq_m_n_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGTQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# gt, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpgtq_m_s]) -;; -(define_insn "mve_vcmpgtq_m_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGTQ_M_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# gt, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmphiq_m_n_u]) -;; -(define_insn "mve_vcmphiq_m_n_u" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPHIQ_M_N_U)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.u%# hi, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmphiq_m_u]) -;; -(define_insn "mve_vcmphiq_m_u" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPHIQ_M_U)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.u%# hi, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpleq_m_n_s]) -;; -(define_insn "mve_vcmpleq_m_n_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLEQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# le, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpleq_m_s]) -;; -(define_insn "mve_vcmpleq_m_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLEQ_M_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# le, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpltq_m_n_s]) -;; -(define_insn "mve_vcmpltq_m_n_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLTQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# lt, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpltq_m_s]) -;; -(define_insn "mve_vcmpltq_m_s" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLTQ_M_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vcmpt.s%# lt, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpneq_m_n_u, vcmpneq_m_n_s]) ;; -(define_insn "mve_vcmpneq_m_n_" +(define_insn "@mve_vcmpq_m_n_" [ (set (match_operand: 0 "vpr_register_operand" "=Up") (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r") (match_operand: 3 "vpr_register_operand" "Up")] - VCMPNEQ_M_N)) + MVE_CMP_M_N)) ] "TARGET_HAVE_MVE" - "vpst\;vcmpt.i%# ne, %q1, %2" + "vpst\;vcmpt.%#\t, %q1, %2" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; -;; [vcmpneq_m_s, vcmpneq_m_u]) +;; [vcmpcsq_m_u] +;; [vcmpeqq_m_u, vcmpeqq_m_s] +;; [vcmpgeq_m_s] +;; [vcmpgtq_m_s] +;; [vcmphiq_m_u] +;; [vcmpleq_m_s] +;; [vcmpltq_m_s] +;; [vcmpneq_m_s, vcmpneq_m_u] ;; -(define_insn "mve_vcmpneq_m_" +(define_insn "@mve_vcmpq_m_" [ (set (match_operand: 0 "vpr_register_operand" "=Up") (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VCMPNEQ_M)) + MVE_CMP_M)) ] "TARGET_HAVE_MVE" - "vpst\;vcmpt.i%# ne, %q1, %q2" + "vpst\;vcmpt.%#\t, %q1, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -2785,177 +2580,22 @@ ;; ;; [vcmpeqq_m_n_f]) -;; -(define_insn "mve_vcmpeqq_m_n_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPEQQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# eq, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpgeq_m_f]) -;; -(define_insn "mve_vcmpgeq_m_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGEQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# ge, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpgeq_m_n_f]) -;; -(define_insn "mve_vcmpgeq_m_n_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGEQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# ge, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpgtq_m_f]) -;; -(define_insn "mve_vcmpgtq_m_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGTQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# gt, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpgtq_m_n_f]) -;; -(define_insn "mve_vcmpgtq_m_n_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPGTQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# gt, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpleq_m_f]) -;; -(define_insn "mve_vcmpleq_m_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLEQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# le, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpleq_m_n_f]) -;; -(define_insn "mve_vcmpleq_m_n_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLEQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# le, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpltq_m_f]) -;; -(define_insn "mve_vcmpltq_m_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLTQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# lt, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpltq_m_n_f]) -;; -(define_insn "mve_vcmpltq_m_n_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPLTQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# lt, %q1, %2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmpneq_m_f]) -;; -(define_insn "mve_vcmpneq_m_f" - [ - (set (match_operand: 0 "vpr_register_operand" "=Up") - (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCMPNEQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# ne, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vcmpneq_m_n_f]) ;; -(define_insn "mve_vcmpneq_m_n_f" +(define_insn "@mve_vcmpq_m_n_f" [ (set (match_operand: 0 "vpr_register_operand" "=Up") (unspec: [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r") (match_operand: 3 "vpr_register_operand" "Up")] - VCMPNEQ_M_N_F)) + MVE_CMP_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmpt.f%# ne, %q1, %2" + "vpst\;vcmpt.f%#\t, %q1, %2" [(set_attr "type" "mve_move") (set_attr "length""8")]) -- 2.47.2