From 6a1e018fa43fec1aa455c4b407a35095b0012cde Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 22 Jun 2018 22:48:57 +0200 Subject: [PATCH] backport: re PR target/84899 (ICE: in final_scan_insn_1, at final.c:3139 (error: could not split insn)) Backported from mainline 2018-03-16 Jakub Jelinek PR target/84899 * postreload.c (reload_combine_recognize_pattern): Perform INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and truncate_int_for_mode the result for the destination's mode. * gcc.dg/pr84899.c: New test. From-SVN: r261929 --- gcc/ChangeLog | 5 +++++ gcc/postreload.c | 12 +++++++----- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.dg/pr84899.c | 12 ++++++++++++ 4 files changed, 27 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr84899.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d3d6ec7a6db2..6ac9e4082516 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -3,6 +3,11 @@ Backported from mainline 2018-03-16 Jakub Jelinek + PR target/84899 + * postreload.c (reload_combine_recognize_pattern): Perform + INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and + truncate_int_for_mode the result for the destination's mode. + PR tree-optimization/84841 * tree-ssa-reassoc.c (INTEGER_CONST_TYPE): Change to 1 << 4 from 1 << 3. diff --git a/gcc/postreload.c b/gcc/postreload.c index e721f2f867da..d60875a257b4 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -1160,11 +1160,13 @@ reload_combine_recognize_pattern (rtx_insn *insn) value in PREV, the constant loading instruction. */ validate_change (prev, &SET_DEST (prev_set), index_reg, 1); if (reg_state[regno].offset != const0_rtx) - validate_change (prev, - &SET_SRC (prev_set), - GEN_INT (INTVAL (SET_SRC (prev_set)) - + INTVAL (reg_state[regno].offset)), - 1); + { + HOST_WIDE_INT c + = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set)) + + UINTVAL (reg_state[regno].offset), + GET_MODE (index_reg)); + validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1); + } /* Now for every use of REG that we have recorded, replace REG with REG_SUM. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0a2d4686ff60..9580923bb6cd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -3,6 +3,9 @@ Backported from mainline 2018-03-16 Jakub Jelinek + PR target/84899 + * gcc.dg/pr84899.c: New test. + PR c++/84874 * g++.dg/cpp1z/desig8.C: New test. diff --git a/gcc/testsuite/gcc.dg/pr84899.c b/gcc/testsuite/gcc.dg/pr84899.c new file mode 100644 index 000000000000..0706fecada39 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr84899.c @@ -0,0 +1,12 @@ +/* PR target/84899 */ +/* { dg-do compile } */ +/* { dg-options "-O -funroll-all-loops -fno-move-loop-invariants" } */ + +void +foo (int x) +{ + int a = 1 / x, b = 0; + + while ((a + b + 1) < x) + b = __INT_MAX__; +} -- 2.47.2