From 6aff357efc2bb060e5b400774becfd3d37644b44 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 18 Oct 2024 14:02:15 +0100 Subject: [PATCH] clk: samsung: gs101: make all ufs related clocks critical Enabling UFSHCD_CAP_HIBERN8_WITH_CLK_GATING in the UFS driver means all UFS clocks are gated/ungated, which leads to the UFS IP getting into a bad state and being completely non functional. Downstream these clocks are all left in Automatic Clock Gate (ACG) mode, and are not exposed to the UFS driver in DT. Enabling ACG is ultimately what we need to do in the upstream Samsung clock driver as well. However until ACG is enabled upstream, we mark these clocks as critical to avoid them being disabled. This then allow us to enable UFSHCD_CAP_HIBERN8_WITH_CLK_GATING and have UFS hibern8. Whilst this may seem at first glance a strange thing to do, the clocks between UFS host and UFS device are still gated after this change, and enabling UFS hibern8 leads to substantially cooler device when running the upstream kernel on a Pixel 6 phone. This change only effects the clocks from the CMU to the UFS IP. Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20241018130215.487425-1-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-gs101.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 85098c61c15e6..86b39edba1227 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2775,11 +2775,11 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK, "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, - 21, 0, 0), + 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK, "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, - 21, 0, 0), + 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK, "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, @@ -2806,7 +2806,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK, "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, - 21, 0, 0), + 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK, "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, @@ -2842,7 +2842,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK, "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, - 21, 0, 0), + 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO, "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, @@ -2850,7 +2850,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK, "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, - 21, 0, 0), + 21, CLK_IS_CRITICAL, 0), /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK, "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user", -- 2.47.2