From 6b2ff1d7c57ef49cd17ffe132173e05ab11a5213 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Mon, 12 Jan 2026 14:03:30 -0800 Subject: [PATCH] drm/xe: vram addr range is expanded to bit[17:8] The bit field used to be [14:8] with [17:15] marked as SPARE and defaulted to 0. So, simply expand the read to bit[17:8] assuming the platforms using only bit[14:8] have zeros in the expanded bits. BSpec: 54991 Signed-off-by: Fei Yang Reviewed-by: Matthew Brost Signed-off-by: Matthew Brost Link: https://patch.msgid.link/20260112220330.2267122-2-fei.yang@intel.com --- drivers/gpu/drm/xe/xe_vram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index c64d98bf1723..4f807eade2b7 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -155,7 +155,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, *tile_offset = 0; } else { reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); - *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; + *tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G; *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; } -- 2.47.3